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Searched refs:pll0_div (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/clk/renesas/
Drenesas-cpg-mssr.h30 unsigned int pll0_div; member
Dr8a7792-cpg-mssr.c219 .pll0_div = 2,
Dr8a7794-cpg-mssr.c248 .pll0_div = 2,
Dr8a7791-cpg-mssr.c267 .pll0_div = 2,
Dr8a7790-cpg-mssr.c271 .pll0_div = 2,
Dclk-rcar-gen2.c153 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div; in gen2_clk_get_rate()