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Searched refs:pll1_cfg (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Dclock_sun4i.c30 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
95 u32 pll1_cfg; member
169 writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); in clock_set_pll1()
Dclock_sun6i.c137 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); in clock_set_pll1()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dclock_sun4i.h14 u32 pll1_cfg; /* 0x00 pll1 control */ member
Dclock_sun6i.h14 u32 pll1_cfg; /* 0x00 pll1 control */ member