Searched refs:pll1_ctrl (Results 1 – 6 of 6) sorted by relevance
18 writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), in enable_pll1()19 &stv0991_cgu_regs->pll1_ctrl); in enable_pll1()
34 u32 pll1_ctrl; /* offset 0x64 */ member
102 u32 pll1_ctrl; member
298 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, in clock_init()
439 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, in clock_init()
492 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, in clock_init()