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Searched refs:prcm (Results 1 – 25 of 34) sorted by relevance

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/external/u-boot/arch/arm/mach-omap2/omap5/
Dhw_data.c21 struct prcm_regs const **prcm = variable
386 (*prcm)->cm_l4per_clkstctrl, in enable_basic_clocks()
387 (*prcm)->cm_l3init_clkstctrl, in enable_basic_clocks()
388 (*prcm)->cm_memif_clkstctrl, in enable_basic_clocks()
389 (*prcm)->cm_l4cfg_clkstctrl, in enable_basic_clocks()
391 (*prcm)->cm_gmac_clkstctrl, in enable_basic_clocks()
397 (*prcm)->cm_l3_gpmc_clkctrl, in enable_basic_clocks()
398 (*prcm)->cm_memif_emif_1_clkctrl, in enable_basic_clocks()
399 (*prcm)->cm_memif_emif_2_clkctrl, in enable_basic_clocks()
400 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, in enable_basic_clocks()
[all …]
Dhwinit.c219 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
221 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
273 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
275 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
277 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); in srcomp_enable()
279 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); in srcomp_enable()
427 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); in reset_cpu()
429 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); in reset_cpu()
434 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; in warm_reset()
452 rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; in setup_warmreset_time()
[all …]
Ddra7xx_iodelay.c28 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
31 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
41 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
45 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
DMakefile10 obj-y += prcm-regs.o
/external/u-boot/arch/arm/mach-omap2/omap4/
Dhw_data.c19 struct prcm_regs const **prcm = variable
331 (*prcm)->cm_l4per_clkstctrl, in enable_basic_clocks()
332 (*prcm)->cm_l3init_clkstctrl, in enable_basic_clocks()
333 (*prcm)->cm_memif_clkstctrl, in enable_basic_clocks()
334 (*prcm)->cm_l4cfg_clkstctrl, in enable_basic_clocks()
339 (*prcm)->cm_l3_gpmc_clkctrl, in enable_basic_clocks()
340 (*prcm)->cm_memif_emif_1_clkctrl, in enable_basic_clocks()
341 (*prcm)->cm_memif_emif_2_clkctrl, in enable_basic_clocks()
342 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, in enable_basic_clocks()
343 (*prcm)->cm_wkup_gpio1_clkctrl, in enable_basic_clocks()
[all …]
DMakefile10 obj-y += prcm-regs.o
/external/u-boot/arch/arm/mach-omap2/
Dclocks-common.c58 ind = (readl((*prcm)->cm_sys_clksel) & in __get_sys_clk_index()
327 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); in configure_mpu_dpll()
328 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); in configure_mpu_dpll()
329 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, in configure_mpu_dpll()
331 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, in configure_mpu_dpll()
339 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); in configure_mpu_dpll()
364 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, in setup_usb_dpll()
369 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); in setup_usb_dpll()
390 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, in setup_dplls()
393 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, in setup_dplls()
[all …]
Dvc.c77 writel(val, (*prcm)->prm_vc_cfg_i2c_clk); in omap_vc_init()
85 writel(val, (*prcm)->prm_vc_cfg_i2c_mode); in omap_vc_init()
111 writel(reg_val, (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
115 (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
119 reg_val = readl((*prcm)->prm_vc_val_bypass) & in omap_vc_bypass_send_value()
Demif-common.c1470 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1471 __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1488 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1524 bypass_dpll((*prcm)->cm_clkmode_dpll_core); in sdram_init()
1526 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); in sdram_init()
/external/u-boot/arch/arm/mach-omap2/omap3/
Dclock.c30 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in get_osc_clk_speed()
121 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll3_init_34xx()
233 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll4_init_34xx()
286 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll5_init_34xx()
310 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in mpu_init_34xx()
337 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in iva_init_34xx()
378 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll3_init_36xx()
483 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll4_init_36xx()
526 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll5_init_36xx()
548 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in mpu_init_36xx()
[all …]
Dboard.c251 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in watchdog_init()
DMakefile15 obj-y += prcm-regs.o
/external/u-boot/arch/arm/mach-sunxi/
Dprcm.c26 struct sunxi_prcm_reg *prcm = in prcm_apb0_enable() local
30 setbits_le32(&prcm->apb0_gate, flags); in prcm_apb0_enable()
33 setbits_le32(&prcm->apb0_reset, flags); in prcm_apb0_enable()
38 struct sunxi_prcm_reg *prcm = in prcm_apb0_disable() local
42 clrbits_le32(&prcm->apb0_reset, flags); in prcm_apb0_disable()
45 clrbits_le32(&prcm->apb0_gate, flags); in prcm_apb0_disable()
Dclock_sun6i.c25 struct sunxi_prcm_reg * const prcm = in clock_init_safe() local
29 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, in clock_init_safe()
31 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, in clock_init_safe()
34 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); in clock_init_safe()
68 struct sunxi_prcm_reg * const prcm = in clock_init_sec() local
75 setbits_le32(&prcm->prcm_sec_switch, in clock_init_sec()
DMakefile15 obj-$(CONFIG_SUN6I_PRCM) += prcm.o
/external/u-boot/board/ti/omap5_uevm/
Devm.c165 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); in enable_host_clocks()
168 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, in enable_host_clocks()
172 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, in enable_host_clocks()
176 auxclk = readl((*prcm)->scrm_auxclk1); in enable_host_clocks()
179 writel(auxclk, (*prcm)->scrm_auxclk1); in enable_host_clocks()
/external/u-boot/board/compulab/cm_t54/
Dcm_t54.c207 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); in setup_host_clocks()
209 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); in setup_host_clocks()
214 clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); in setup_host_clocks()
215 clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); in setup_host_clocks()
/external/u-boot/board/htkw/mcx/
Dmcx.c126 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in board_video_init()
/external/u-boot/arch/arm/cpu/armv7/sunxi/
Dpsci.c160 struct sunxi_prcm_reg *prcm = in sunxi_cpu_set_power() local
163 sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, in sunxi_cpu_set_power()
/external/u-boot/board/compulab/common/
Domap3_display.c398 struct prcm *prcm = (struct prcm *)PRCM_BASE; in lcd_ctrl_init() local
421 clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); in lcd_ctrl_init()
/external/u-boot/drivers/usb/phy/
Domap_usb_phy.c197 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, in omap_enable_usb2_phy2()
200 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, in omap_enable_usb2_phy2()
/external/u-boot/board/teejet/mt_ventoux/
Dmt_ventoux.c304 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in board_video_init()
/external/u-boot/arch/arm/mach-omap2/am33xx/
DMakefile22 obj-y += prcm-regs.o
/external/u-boot/arch/arm/dts/
Ddm816x.dtsi69 prcm: prcm@48180000 { label
70 compatible = "ti,dm816-prcm";
/external/u-boot/board/compulab/cl-som-am57x/
Dspl.c208 *prcm = &dra7xx_prcm; in hw_data_init()

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