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Searched refs:preop (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.trig.preop.ll4 declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone
15 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone
27 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.trig.preop.ll4 declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone
15 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone
27 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone
/external/u-boot/drivers/spi/
Dich.c137 ctlr->preop = offsetof(struct ich7_spi_regs, preop); in ich_init_controller()
152 ctlr->preop = offsetof(struct ich9_spi_regs, preop); in ich_init_controller()
362 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); in ich_spi_config_opcode()
460 ich_writew(ctlr, trans->opcode, ctlr->preop); in ich_spi_xfer()
486 if (ich_readw(ctlr, ctlr->preop)) in ich_spi_xfer()
579 ich_writew(ctlr, 0, ctlr->preop); in ich_spi_xfer()
Dich.h18 uint16_t preop; member
37 uint16_t preop; /* 0x94 */ member
183 int preop; member
/external/clang/test/CodeGenOpenCL/
Dbuiltins-amdgcn.cl63 // CHECK: call float @llvm.amdgcn.trig.preop.f32
70 // CHECK: call double @llvm.amdgcn.trig.preop.f64
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td157 // Special case divide preop and flags.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td257 // Special case divide preop and flags.
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc969 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
DIntrinsicImpl.inc995 "llvm.amdgcn.trig.preop",
9873 4, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen513 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6537 "llvm.amdgcn.trig.preop",
14422 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop