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Searched refs:pu1_avail (Results 1 – 13 of 13) sorted by relevance

/external/libhevc/common/
Dihevc_sao.c193 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class0() argument
222 if(0 == pu1_avail[0]) in ihevc_sao_edge_offset_class0()
226 if(0 == pu1_avail[1]) in ihevc_sao_edge_offset_class0()
275 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class0_chroma() argument
308 if(0 == pu1_avail[0]) in ihevc_sao_edge_offset_class0_chroma()
312 if(0 == pu1_avail[1]) in ihevc_sao_edge_offset_class0_chroma()
372 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class1() argument
403 if(0 == pu1_avail[2]) in ihevc_sao_edge_offset_class1()
419 if(0 == pu1_avail[3]) in ihevc_sao_edge_offset_class1()
465 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class1_chroma() argument
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Dihevc_sao.h105 UWORD8 *pu1_avail,
117 UWORD8 *pu1_avail,
130 UWORD8 *pu1_avail,
143 UWORD8 *pu1_avail,
157 UWORD8 *pu1_avail,
169 UWORD8 *pu1_avail,
182 UWORD8 *pu1_avail,
195 UWORD8 *pu1_avail,
209 UWORD8 *pu1_avail,
221 UWORD8 *pu1_avail,
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/external/libhevc/common/arm/
Dihevc_sao_edge_offset_class3.s46 @ UWORD8 *pu1_avail,
56 @r5 => *pu1_avail
101 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
118 LDRB r9,[r5,#5] @pu1_avail[5]
155 LDRB r10,[r5,#6] @pu1_avail[6]
203 LDRB r11,[r5,#3] @pu1_avail[3]
209 LDRB r5,[r5,#2] @pu1_avail[2]
235 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
237 LDRBEQ r8,[r5] @pu1_avail[0]
243 LDRB r8,[r5,#1] @pu1_avail[1]
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Dihevc_sao_edge_offset_class3_chroma.s46 @ UWORD8 *pu1_avail,
57 @r5 => *pu1_avail
110 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
127 LDRB r9,[r5,#5] @pu1_avail[5]
195 LDRB r10,[r5,#6] @pu1_avail[6]
269 LDRB r11,[r5,#3] @pu1_avail[3]
275 LDRB r5,[r5,#2] @pu1_avail[2]
306 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
308 LDRBEQ r8,[r5] @pu1_avail[0]
312 LDRB r11,[r5,#2] @pu1_avail[2]
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Dihevc_sao_edge_offset_class2.s46 @ UWORD8 *pu1_avail,
56 @r5 => *pu1_avail
103 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
120 LDRB r10,[r5,#4] @pu1_avail[4]
152 LDRB r14,[r5,#7] @pu1_avail[7]
191 LDRB r11,[r5,#3] @pu1_avail[3]
197 LDRB r5,[r5,#2] @pu1_avail[2]
225 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
227 LDRBEQ r8,[r5] @pu1_avail[0]
230 … VMOV.8 d8[0],r8 @au1_mask = vsetq_lane_s8((-1||pu1_avail[0]), au1_mask, 0)
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Dihevc_sao_edge_offset_class0_chroma.s46 @ UWORD8 *pu1_avail,
57 @r7 => *pu1_avail
96 LDR r7,[sp,#pu1_avail_offset] @Loads pu1_avail
136 LDRB r12,[r7] @pu1_avail[0]
137 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
138 VMOV.8 D8[1],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 1)
148 LDRB r12,[r7,#1] @pu1_avail[1]
149 VMOV.8 D9[6],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 14)
150 VMOV.8 D9[7],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
302 LDRB r12,[r7] @pu1_avail[0]
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Dihevc_sao_edge_offset_class2_chroma.s46 @ UWORD8 *pu1_avail,
57 @r5 => *pu1_avail
112 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
129 LDRB r9,[r5,#4] @pu1_avail[4]
200 LDRB r10,[r5,#7] @pu1_avail[7]
280 LDRB r11,[r5,#3] @pu1_avail[3]
285 LDRB r5,[r5,#2] @pu1_avail[2]
311 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
314 LDRBEQ r8,[r5] @pu1_avail[0]
323 LDRB r8,[r5,#1] @pu1_avail[1]
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Dihevc_sao_edge_offset_class1.s46 @ UWORD8 *pu1_avail,
56 @r5 => *pu1_avail
86 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
106 LDRB r4,[r5,#2] @pu1_avail[2]
107 CMP r4,#0 @0 == pu1_avail[2]
111 LDRB r4,[r5,#3] @pu1_avail[3]
112 CMP r4,#0 @0 == pu1_avail[3]
128 LDRB r4,[r5,#2] @pu1_avail[2]
129 CMP r4,#0 @0 == pu1_avail[2]
228 BEQ PU1_SRC_LOOP_END @if 0 == pu1_avail[3] || 0 == pu1_avail[2] ht = ht--
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Dihevc_sao_edge_offset_class0.s46 @ UWORD8 *pu1_avail,
57 @r7 => *pu1_avail
95 LDR r7,[sp,#pu1_avail_offset] @Loads pu1_avail
131 LDRB r12,[r7] @pu1_avail[0]
132 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
142 LDRB r12,[r7,#1] @pu1_avail[1]
143 VMOV.8 D9[7],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
283 LDRB r12,[r7] @pu1_avail[0]
284 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
292 LDRB r11,[r7,#1] @pu1_avail[1]
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Dihevc_sao_edge_offset_class1_chroma.s46 @ UWORD8 *pu1_avail,
57 @r5 => *pu1_avail
87 LDR r5,[sp,#pu1_avail_offset] @Loads pu1_avail
109 LDRB r4,[r5,#2] @pu1_avail[2]
110 CMP r4,#0 @0 == pu1_avail[2]
114 LDRB r4,[r5,#3] @pu1_avail[3]
115 CMP r4,#0 @0 == pu1_avail[3]
132 LDRB r4,[r5,#2] @pu1_avail[2]
133 CMP r4,#0 @0 == pu1_avail[2]
240 BEQ PU1_SRC_LOOP_END @if 0 == pu1_avail[3] || 0 == pu1_avail[2] ht = ht--
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/external/libhevc/encoder/
Dihevce_sao.c119 UWORD8 *pu1_avail, sao_ctxt_t *ps_sao_ctxt, ihevce_tile_params_t *ps_tile_params) in ihevce_sao_set_avilability() argument
128 pu1_avail[i] = 255; in ihevce_sao_set_avilability()
140 pu1_avail[0] = 0; in ihevce_sao_set_avilability()
141 pu1_avail[4] = 0; in ihevce_sao_set_avilability()
142 pu1_avail[6] = 0; in ihevce_sao_set_avilability()
149 pu1_avail[1] = 0; in ihevce_sao_set_avilability()
150 pu1_avail[5] = 0; in ihevce_sao_set_avilability()
151 pu1_avail[7] = 0; in ihevce_sao_set_avilability()
157 pu1_avail[2] = 0; in ihevce_sao_set_avilability()
158 pu1_avail[4] = 0; in ihevce_sao_set_avilability()
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Dihevce_enc_loop_structs.h301 UWORD8 *pu1_avail,
315 UWORD8 *pu1_avail,
/external/libhevc/common/x86/
Dihevc_sao_ssse3_intr.c884 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class0_ssse3() argument
932 u1_avail0 = pu1_avail[0]; in ihevc_sao_edge_offset_class0_ssse3()
933 u1_avail1 = pu1_avail[1]; in ihevc_sao_edge_offset_class0_ssse3()
1218 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class0_chroma_ssse3() argument
1270 u1_avail0 = pu1_avail[0]; in ihevc_sao_edge_offset_class0_chroma_ssse3()
1271 u1_avail1 = pu1_avail[1]; in ihevc_sao_edge_offset_class0_chroma_ssse3()
1589 UWORD8 *pu1_avail, in ihevc_sao_edge_offset_class1_ssse3() argument
1626 if(0 == pu1_avail[2]) in ihevc_sao_edge_offset_class1_ssse3()
1632 if(0 == pu1_avail[3]) in ihevc_sao_edge_offset_class1_ssse3()
1765 if(0 == pu1_avail[3]) in ihevc_sao_edge_offset_class1_ssse3()
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