| /external/arm-neon-tests/ |
| D | ref_dsp.c | 156 sres = qdadd(svar1, svar2); in exec_dsp()
162 sres = qdadd(svar1, svar2); in exec_dsp()
168 sres = qdadd(svar1, svar2); in exec_dsp()
174 sres = qdadd(svar1, svar2); in exec_dsp()
180 sres = qdadd(svar1, svar2); in exec_dsp()
186 sres = qdadd(svar1, svar2); in exec_dsp()
192 sres = qdadd(svar1, svar2); in exec_dsp()
198 sres = qdadd(svar1, svar2); in exec_dsp()
204 sres = qdadd(svar1, svar2); in exec_dsp()
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| D | ref-rvct-all.txt | 7988 qdadd(0x1, 0x2) = 0x5 sat 0
7989 qdadd(0xffffffff, 0xfffffffe) = 0xfffffffb sat 0
7990 qdadd(0xffffffff, 0x2) = 0x3 sat 0
7991 qdadd(0x7000, 0x7000) = 0x15000 sat 0
7992 qdadd(0x8fff, 0x8fff) = 0x1affd sat 0
7993 qdadd(0x70000000, 0x70000000) = 0x7fffffff sat 1
7994 qdadd(0, 0x70000000) = 0x7fffffff sat 1
7995 qdadd(0x8fffffff, 0x8fffffff) = 0x80000000 sat 1
7996 qdadd(0, 0x8fffffff) = 0x80000000 sat 1
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 81 define i32 @qdadd(i32 %a, i32 %b) nounwind {
82 ; CHECK-LABEL: qdadd
83 ; CHECK: qdadd r0, r0, r1
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 107 M(qdadd) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 106 M(qdadd) \
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 496 0x57,0x60,0x48,0xe1 = qdadd r6, r7, r8
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| D | basic-thumb2-instructions.s.cs | 591 0x88,0xfa,0x97,0xf6 = qdadd r6, r7, r8
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1198 qdadd r6, r7, r8
1203 @ CHECK: qdadd r6, r7, r8 @ encoding: [0x57,0x60,0x48,0xe1]
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| D | basic-thumb2-instructions.s | 1447 qdadd r6, r7, r8
1453 @ CHECK: qdadd r6, r7, r8 @ encoding: [0x88,0xfa,0x97,0xf6]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2836 void qdadd(Condition cond, Register rd, Register rm, Register rn);
2837 void qdadd(Register rd, Register rm, Register rn) { qdadd(al, rd, rm, rn); } in qdadd() function
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| D | disasm-aarch32.h | 996 void qdadd(Condition cond, Register rd, Register rm, Register rn);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1922 qdadd r6, r7, r8
1928 @ CHECK: qdadd r6, r7, r8 @ encoding: [0x88,0xfa,0x97,0xf6]
|
| D | basic-arm-instructions.s | 1807 qdadd r6, r7, r8
1812 @ CHECK: qdadd r6, r7, r8 @ encoding: [0x57,0x60,0x48,0xe1]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1805 qdadd r6, r7, r8
1810 @ CHECK: qdadd r6, r7, r8 @ encoding: [0x57,0x60,0x48,0xe1]
|
| D | basic-thumb2-instructions.s | 1874 qdadd r6, r7, r8
1880 @ CHECK: qdadd r6, r7, r8 @ encoding: [0x88,0xfa,0x97,0xf6]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1034 # CHECK: qdadd r6, r7, r8
|
| D | thumb2.txt | 1247 # CHECK: qdadd r6, r7, r8
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1386 # CHECK: qdadd r6, r7, r8
|
| D | basic-arm-instructions.txt | 1151 # CHECK: qdadd r6, r7, r8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1151 # CHECK: qdadd r6, r7, r8
|
| D | thumb2.txt | 1386 # CHECK: qdadd r6, r7, r8
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1936 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
|
| D | ARMInstrInfo.td | 3166 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2214 def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2141 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
|