| /external/arm-neon-tests/ |
| D | ref_dsp.c | 212 sres = qdsub(svar1, svar2); in exec_dsp()
218 sres = qdsub(svar1, svar2); in exec_dsp()
224 sres = qdsub(svar1, svar2); in exec_dsp()
230 sres = qdsub(svar1, svar2); in exec_dsp()
236 sres = qdsub(svar1, svar2); in exec_dsp()
242 sres = qdsub(svar1, svar2); in exec_dsp()
248 sres = qdsub(svar1, svar2); in exec_dsp()
254 sres = qdsub(svar1, svar2); in exec_dsp()
260 sres = qdsub(svar1, svar2); in exec_dsp()
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| D | ref-rvct-all.txt | 7997 qdsub(0x1, 0x2) = 0xfffffffd sat 0
7998 qdsub(0xffffffff, 0xfffffffe) = 0x3 sat 0
7999 qdsub(0xffffffff, 0x2) = 0xfffffffb sat 0
8000 qdsub(0x7000, 0xffff9000) = 0x15000 sat 0
8001 qdsub(0x8fff, 0xffff7001) = 0x1affd sat 0
8002 qdsub(0x70000000, 0x90000000) = 0x7fffffff sat 1
8003 qdsub(0, 0x90000000) = 0x7fffffff sat 1
8004 qdsub(0x8fffffff, 0x70000001) = 0x80000000 sat 1
8005 qdsub(0, 0x70000001) = 0x80000001 sat 1
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 89 define i32 @qdsub(i32 %a, i32 %b) nounwind {
90 ; CHECK-LABEL: qdsub
91 ; CHECK: qdsub r0, r0, r1
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 108 M(qdsub) \
|
| D | test-assembler-cond-rd-rn-rm-t32.cc | 107 M(qdsub) \
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 498 0x57,0x60,0x68,0xe1 = qdsub r6, r7, r8
|
| D | basic-thumb2-instructions.s.cs | 592 0x88,0xfa,0xb7,0xf6 = qdsub r6, r7, r8
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1200 qdsub r6, r7, r8
1205 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x57,0x60,0x68,0xe1]
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| D | basic-thumb2-instructions.s | 1448 qdsub r6, r7, r8
1454 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2839 void qdsub(Condition cond, Register rd, Register rm, Register rn);
2840 void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); } in qdsub() function
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| D | disasm-aarch32.h | 998 void qdsub(Condition cond, Register rd, Register rm, Register rn);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1923 qdsub r6, r7, r8
1929 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6]
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| D | basic-arm-instructions.s | 1809 qdsub r6, r7, r8
1814 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x57,0x60,0x68,0xe1]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1807 qdsub r6, r7, r8
1812 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x57,0x60,0x68,0xe1]
|
| D | basic-thumb2-instructions.s | 1875 qdsub r6, r7, r8
1881 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1036 # CHECK: qdsub r6, r7, r8
|
| D | thumb2.txt | 1248 # CHECK: qdsub r6, r7, r8
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1387 # CHECK: qdsub r6, r7, r8
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| D | basic-arm-instructions.txt | 1153 # CHECK: qdsub r6, r7, r8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1153 # CHECK: qdsub r6, r7, r8
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| D | thumb2.txt | 1387 # CHECK: qdsub r6, r7, r8
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1938 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
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| D | ARMInstrInfo.td | 3169 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2215 def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2143 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
|