| /external/llvm/test/CodeGen/ARM/ |
| D | sat-arith.ll | 14 ; CHECK-LABEL: qsub
15 define i32 @qsub() nounwind {
18 ; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]]
20 %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
61 declare i32 @llvm.arm.qsub(i32, i32) nounwind
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 70 VMULL.S32 q2, d0, d2 @qsub 2nd
73 VMULL.S32 q5, d1, d3 @qsub 1st
101 VMULL.S32 q2, d0, d2 @qsub 2nd
104 VMULL.S32 q5, d1, d3 @qsub 1st
130 VMULL.S32 q2, d0, d2 @qsub 2nd
133 VMULL.S32 q5, d1, d3 @qsub 1st
|
| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 49 VMULL.S32 q2, d0, d2 @qsub 2nd
52 VMULL.S32 q5, d1, d3 @qsub 1st
101 VMULL.S32 q2, d0, d2 @qsub 2nd
104 VMULL.S32 q5, d1, d3 @qsub 1st
|
| /external/arm-neon-tests/ |
| D | ref_dsp.c | 105 sres = qsub(svar1, svar2); in exec_dsp()
111 sres = qsub(svar1, svar2); in exec_dsp()
117 sres = qsub(svar1, svar2); in exec_dsp()
123 sres = qsub(svar1, svar2); in exec_dsp()
129 sres = qsub(svar1, svar2); in exec_dsp()
135 sres = qsub(svar1, svar2); in exec_dsp()
141 sres = qsub(svar1, svar2); in exec_dsp()
147 sres = qsub(svar1, svar2); in exec_dsp()
|
| D | ref-rvct-all.txt | 7980 qsub(0x1, 0x2) = 0xffffffff sat 0
7981 qsub(0xffffffff, 0xfffffffe) = 0x1 sat 0
7982 qsub(0xffffffff, 0x2) = 0xfffffffd sat 0
7983 qsub(0x7000, 0xffff9000) = 0xe000 sat 0
7984 qsub(0x8fff, 0xffff7001) = 0x11ffe sat 0
7985 qsub(0x70000000, 0x90000000) = 0x7fffffff sat 1
7986 qsub(0x8fffffff, 0x70000001) = 0x80000000 sat 1
7987 qsub(0, 0x80000000) = 0x7fffffff sat 1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 74 define i32 @qsub(i32 %a, i32 %b) nounwind {
75 ; CHECK-LABEL: qsub
76 ; CHECK: qsub r0, r0, r1
77 %tmp = call i32 @llvm.arm.qsub(i32 %a, i32 %b)
93 %add = call i32 @llvm.arm.qsub(i32 %a, i32 %dbl)
110 declare i32 @llvm.arm.qsub(i32, i32) nounwind
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 819 qsub, // 9
1105 { 0, 64 }, // qsub
5133 … { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1",…
5146 LaneBitmask(0x00000004), // qsub
8764 &LaneMaskComposeSequences[10], // to qsub
8895 0, // qsub
8996 0, // qsub
9097 0, // qsub
9198 0, // qsub
9299 0, // qsub
[all …]
|
| /external/syzkaller/vendor/github.com/ianlancetaylor/demangle/ |
| D | demangle.go | 1333 if qsub, ok := ret.(*TypeWithQualifiers); ok {
1334 q = mergeQualifiers(q, qsub.Qualifiers)
1335 ret = qsub.Base
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 109 M(qsub)
|
| D | test-assembler-cond-rd-rn-rm-t32.cc | 108 M(qsub)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 32 def qsub : SubRegIndex<64>;
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 502 0x52,0x10,0x23,0xe1 = qsub r1, r2, r3
|
| D | basic-thumb2-instructions.s.cs | 599 0x83,0xfa,0xa2,0xf1 = qsub r1, r2, r3
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1222 qsub r1, r2, r3
1229 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| D | basic-thumb2-instructions.s | 1475 qsub r1, r2, r3
1483 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 32 def qsub : SubRegIndex<64>;
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2845 void qsub(Condition cond, Register rd, Register rm, Register rn);
2846 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } in qsub() function
|
| D | disasm-aarch32.h | 1002 void qsub(Condition cond, Register rd, Register rm, Register rn);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1950 qsub r1, r2, r3
1958 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|
| D | basic-arm-instructions.s | 1831 qsub r1, r2, r3
1838 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1829 qsub r1, r2, r3
1836 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| D | basic-thumb2-instructions.s | 1902 qsub r1, r2, r3
1910 @ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1058 # CHECK: qsub r1, r2, r3
|
| D | thumb2.txt | 1275 # CHECK: qsub r1, r2, r3
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1414 # CHECK: qsub r1, r2, r3
|