| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 193 define i32 @qsub16(i32 %a, i32 %b) nounwind {
194 ; CHECK-LABEL: qsub16
195 ; CHECK: qsub16 r0, r0, r1
196 %tmp = call i32 @llvm.arm.qsub16(i32 %a, i32 %b)
449 declare i32 @llvm.arm.qsub16(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 58 M(qsub16) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 57 M(qsub16) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 504 0x73,0x1f,0x22,0xe6 = qsub16 r1, r2, r3
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| D | basic-thumb2-instructions.s.cs | 600 0xd2,0xfa,0x13,0xf1 = qsub16 r1, r2, r3
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1224 qsub16 r1, r2, r3
1231 @ CHECK: qsub16 r1, r2, r3 @ encoding: [0x73,0x1f,0x22,0xe6]
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| D | basic-thumb2-instructions.s | 1476 qsub16 r1, r2, r3
1484 @ CHECK: qsub16 r1, r2, r3 @ encoding: [0xd2,0xfa,0x13,0xf1]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2848 void qsub16(Condition cond, Register rd, Register rn, Register rm);
2849 void qsub16(Register rd, Register rn, Register rm) { qsub16(al, rd, rn, rm); } in qsub16() function
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| D | disasm-aarch32.h | 1004 void qsub16(Condition cond, Register rd, Register rn, Register rm);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1951 qsub16 r1, r2, r3
1959 @ CHECK: qsub16 r1, r2, r3 @ encoding: [0xd2,0xfa,0x13,0xf1]
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| D | basic-arm-instructions.s | 1833 qsub16 r1, r2, r3
1840 @ CHECK: qsub16 r1, r2, r3 @ encoding: [0x73,0x1f,0x22,0xe6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1831 qsub16 r1, r2, r3
1838 @ CHECK: qsub16 r1, r2, r3 @ encoding: [0x73,0x1f,0x22,0xe6]
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| D | basic-thumb2-instructions.s | 1903 qsub16 r1, r2, r3
1911 @ CHECK: qsub16 r1, r2, r3 @ encoding: [0xd2,0xfa,0x13,0xf1]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1060 # CHECK: qsub16 r1, r2, r3
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| D | thumb2.txt | 1276 # CHECK: qsub16 r1, r2, r3
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1415 # CHECK: qsub16 r1, r2, r3
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| D | basic-arm-instructions.txt | 1177 # CHECK: qsub16 r1, r2, r3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1177 # CHECK: qsub16 r1, r2, r3
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| D | thumb2.txt | 1415 # CHECK: qsub16 r1, r2, r3
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1944 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
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| D | ARMInstrInfo.td | 3177 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2205 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
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| D | ARMInstrInfo.td | 3706 def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2149 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7748 "qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub8\004r"
8541 …{ 722 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|…
8542 …{ 722 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MC…
|