| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 86 define i32 @qsub8(i32 %a, i32 %b) nounwind {
87 ; CHECK-LABEL: qsub8
88 ; CHECK: qsub8 r0, r0, r1
89 %tmp = call i32 @llvm.arm.qsub8(i32 %a, i32 %b)
433 declare i32 @llvm.arm.qsub8(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 59 M(qsub8) \
|
| D | test-assembler-cond-rd-rn-rm-t32.cc | 58 M(qsub8) \
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 506 0xf3,0x1f,0x22,0xe6 = qsub8 r1, r2, r3
|
| D | basic-thumb2-instructions.s.cs | 601 0xc2,0xfa,0x13,0xf1 = qsub8 r1, r2, r3
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1226 qsub8 r1, r2, r3
1233 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xf3,0x1f,0x22,0xe6]
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| D | basic-thumb2-instructions.s | 1477 qsub8 r1, r2, r3
1485 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xc2,0xfa,0x13,0xf1]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2851 void qsub8(Condition cond, Register rd, Register rn, Register rm);
2852 void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); } in qsub8() function
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| D | disasm-aarch32.h | 1006 void qsub8(Condition cond, Register rd, Register rn, Register rm);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1952 qsub8 r1, r2, r3
1960 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xc2,0xfa,0x13,0xf1]
|
| D | basic-arm-instructions.s | 1835 qsub8 r1, r2, r3
1842 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xf3,0x1f,0x22,0xe6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1833 qsub8 r1, r2, r3
1840 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xf3,0x1f,0x22,0xe6]
|
| D | basic-thumb2-instructions.s | 1904 qsub8 r1, r2, r3
1912 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xc2,0xfa,0x13,0xf1]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1062 # CHECK: qsub8 r1, r2, r3
|
| D | thumb2.txt | 1277 # CHECK: qsub8 r1, r2, r3
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1416 # CHECK: qsub8 r1, r2, r3
|
| D | basic-arm-instructions.txt | 1179 # CHECK: qsub8 r1, r2, r3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1179 # CHECK: qsub8 r1, r2, r3
|
| D | thumb2.txt | 1416 # CHECK: qsub8 r1, r2, r3
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1945 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
|
| D | ARMInstrInfo.td | 3178 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2206 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
|
| D | ARMInstrInfo.td | 3707 def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2150 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7748 "qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub8\004r"
8543 …{ 729 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Fe…
8544 …{ 729 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_…
|