| /external/boringssl/linux-x86_64/crypto/fipsmodule/ |
| D | sha512-x86_64.S | 39 pushq %r12
40 .cfi_offset %r12,-32
73 movq 0(%rsi),%r12
76 bswapq %r12
84 movq %r12,0(%rsp)
89 addq %r11,%r12
94 addq %r15,%r12
97 addq (%rbp),%r12
106 addq %r13,%r12
109 addq %r12,%rdx
[all …]
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| /external/boringssl/mac-x86_64/crypto/fipsmodule/ |
| D | sha512-x86_64.S | 38 pushq %r12
72 movq 0(%rsi),%r12
75 bswapq %r12
83 movq %r12,0(%rsp)
88 addq %r11,%r12
93 addq %r15,%r12
96 addq (%rbp),%r12
105 addq %r13,%r12
108 addq %r12,%rdx
109 addq %r12,%r11
[all …]
|
| /external/boringssl/win-x86_64/crypto/fipsmodule/ |
| D | sha512-x86_64.asm | 45 push r12
79 mov r12,QWORD[rsi]
82 bswap r12
90 mov QWORD[rsp],r12
95 add r12,r11
100 add r12,r15
103 add r12,QWORD[rbp]
112 add r12,r13
115 add rdx,r12
116 add r11,r12
[all …]
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_shiftrountine.s | 30 STMFD sp!, {r4-r7, r12}
31 MOV r12, #0x1f
34 CMP r3, r12
35 MOVGT r3, r12
37 @ LDMMIFD sp!, {r4-r7, r12}
38 LDMFDMI sp!, {r4-r7, r12}
41 LDR r12, [r0, #0]
43 MOV r12, r12, ASR r3
45 STR r12, [r0], #4
48 LDR r12, [r0, #0]
[all …]
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| D | ixheaacd_harm_idx_zerotwolp.s | 26 STMFD sp!, {r4-r12}
30 LDR r12, [sp, #48]
36 CMP r12, #0
42 LDR r12, [r0, #0]
47 SMULWB r7, r12, r7
50 LDRH r12, [r3], #4
55 MOVS r12, r12, LSL #16
59 QADDEQ r8, r8, r12
60 QSUBNE r8, r8, r12
68 ADD r12, r10, r2, LSL #2
[all …]
|
| D | ixheaacd_autocorr_st2.s | 26 STMFD sp!, {r4-r12, r14}
74 ADD r12, r1, #64*4
83 LDR r7 , [r12, #4*128]!
97 LDR r5 , [r12, #4*128]!
119 LDR r7 , [r12, #4*128]!
144 MOV r12, r11
151 SMLAWT r12, r6 , r6, r12
154 SMLAWT r12, r7 , r7, r12
171 STR r12, [r0, #4]
186 LDR r12, [r1, #-4*128]
[all …]
|
| D | ixheaacd_aac_ld_dec_rearrange.s | 6 STMFD r13!, {r4 - r12, r14}
28 LDMIA r4, {r12, r14} @ r12 = inp[idx] and r14 = inp[idx+1]
29 STMIA r1!, {r12, r14} @ *buf1++ = inp[idx] and *buf1++ = inp[idx+1]
30 LDMIA r5, {r12, r14} @ r12 = inp[idx] and r14 = inp[idx+1]
31 STMIA r1!, {r12, r14} @ *buf1++ = inp[idx] and *buf1++ = inp[idx+1]
32 LDMIA r6, {r12, r14} @ r12 = inp[idx] and r14 = inp[idx+1]
33 STMIA r1!, {r12, r14} @ *buf1++ = inp[idx] and *buf1++ = inp[idx+1]
34 LDMIA r7, {r12, r14} @ r12 = inp[idx] and r14 = inp[idx+1]
35 STMIA r1!, {r12, r14} @ *buf1++ = inp[idx] and *buf1++ = inp[idx+1]
36 LDMIA r8, {r12, r14} @ r12 = inp[idx] and r14 = inp[idx+1]
[all …]
|
| D | ixheaacd_mps_complex_fft_64_asm.s | 7 STMFD sp!, {r0-r12, lr}
13 SUB r12, r0, #16 @dig_rev_shift = norm32(npoints) + 1 -16@
23 MOV r12, r4
25 LDRB r10, [r12, r0, LSR #2]
61 MOV r12, #0x40 @nodespacing = 64@
62 STR r12, [sp, #0x38]
63 LDR r12, [sp, #0x48]
67 MOV r4, r12, ASR #4
74 LDR r12, [sp, #0x50] @WORD32 *data = ptr_y@
80 LDRD r4, [r12] @r4=x0r, r5=x0i
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-6xx.s | 8 mfibatu %r12, 0
11 mfibatl %r12, 0
14 mfibatu %r12, 1
17 mfibatl %r12, 1
20 mfibatu %r12, 2
23 mfibatl %r12, 2
26 mfibatu %r12, 3
29 mfibatl %r12, 3
32 mtibatu 0, %r12
35 mtibatl 0, %r12
[all …]
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-6xx.s | 8 mfibatu %r12, 0
11 mfibatl %r12, 0
14 mfibatu %r12, 1
17 mfibatl %r12, 1
20 mfibatu %r12, 2
23 mfibatl %r12, 2
26 mfibatu %r12, 3
29 mfibatl %r12, 3
32 mtibatu 0, %r12
35 mtibatl 0, %r12
[all …]
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| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | aes-armv4.S | 193 stmdb sp!,{r1,r4-r12,lr}
199 mov r12,r0 @ inp
202 ldrb r0,[r12,#3] @ load input data in endian-neutral
203 ldrb r4,[r12,#2] @ manner...
204 ldrb r5,[r12,#1]
205 ldrb r6,[r12,#0]
207 ldrb r1,[r12,#7]
209 ldrb r4,[r12,#6]
211 ldrb r5,[r12,#5]
212 ldrb r6,[r12,#4]
[all …]
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | aes-armv4.S | 194 stmdb sp!,{r1,r4-r12,lr}
200 mov r12,r0 @ inp
203 ldrb r0,[r12,#3] @ load input data in endian-neutral
204 ldrb r4,[r12,#2] @ manner...
205 ldrb r5,[r12,#1]
206 ldrb r6,[r12,#0]
208 ldrb r1,[r12,#7]
210 ldrb r4,[r12,#6]
212 ldrb r5,[r12,#5]
213 ldrb r6,[r12,#4]
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-rd-rn-rm-a32.cc | 100 {{{r2, r10, r12}, false, al, "r2 r10 r12", "r2_r10_r12"},
105 {{r12, r3, r1}, false, al, "r12 r3 r1", "r12_r3_r1"},
115 {{r12, r12, r9}, false, al, "r12 r12 r9", "r12_r12_r9"},
116 {{r12, r10, r12}, false, al, "r12 r10 r12", "r12_r10_r12"},
117 {{r4, r10, r12}, false, al, "r4 r10 r12", "r4_r10_r12"},
119 {{r11, r12, r2}, false, al, "r11 r12 r2", "r11_r12_r2"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
122 {{r12, r8, r4}, false, al, "r12 r8 r4", "r12_r8_r4"},
128 {{r7, r12, r0}, false, al, "r7 r12 r0", "r7_r12_r0"},
135 {{r8, r12, r13}, false, al, "r8 r12 r13", "r8_r12_r13"},
[all …]
|
| D | test-assembler-rd-rn-rm-t32.cc | 100 {{{r2, r10, r12}, false, al, "r2 r10 r12", "r2_r10_r12"},
105 {{r12, r3, r1}, false, al, "r12 r3 r1", "r12_r3_r1"},
115 {{r12, r12, r9}, false, al, "r12 r12 r9", "r12_r12_r9"},
116 {{r12, r10, r12}, false, al, "r12 r10 r12", "r12_r10_r12"},
117 {{r4, r10, r12}, false, al, "r4 r10 r12", "r4_r10_r12"},
119 {{r11, r12, r2}, false, al, "r11 r12 r2", "r11_r12_r2"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
122 {{r12, r8, r4}, false, al, "r12 r8 r4", "r12_r8_r4"},
128 {{r7, r12, r0}, false, al, "r7 r12 r0", "r7_r12_r0"},
135 {{r8, r12, r13}, false, al, "r8 r12 r13", "r8_r12_r13"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-a32.cc | 94 const TestData kTests[] = {{{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
95 {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
102 {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
103 {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
109 {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
130 {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
135 {{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
137 {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
141 {{le, r10, r12}, "le, r10, r12", "le_r10_r12"},
145 {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-t32.cc | 94 const TestData kTests[] = {{{cs, r12, r1}, "cs, r12, r1", "cs_r12_r1"},
95 {{hi, r6, r12}, "hi, r6, r12", "hi_r6_r12"},
102 {{pl, r4, r12}, "pl, r4, r12", "pl_r4_r12"},
103 {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
109 {{al, r3, r12}, "al, r3, r12", "al_r3_r12"},
130 {{ge, r12, r2}, "ge, r12, r2", "ge_r12_r2"},
135 {{lt, r13, r12}, "lt, r13, r12", "lt_r13_r12"},
137 {{mi, r12, r14}, "mi, r12, r14", "mi_r12_r14"},
141 {{le, r10, r12}, "le, r10, r12", "le_r10_r12"},
145 {{lt, r7, r12}, "lt, r7, r12", "lt_r7_r12"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc | 103 {{hi, r12, r12, r2}, true, hi, "hi r12 r12 r2", "hi_r12_r12_r2"},
107 {{ge, r7, r7, r12}, true, ge, "ge r7 r7 r12", "ge_r7_r7_r12"},
113 {{gt, r7, r7, r12}, true, gt, "gt r7 r7 r12", "gt_r7_r7_r12"},
116 {{ge, r12, r12, r2}, true, ge, "ge r12 r12 r2", "ge_r12_r12_r2"},
119 {{gt, r12, r12, r5}, true, gt, "gt r12 r12 r5", "gt_r12_r12_r5"},
125 {{ge, r3, r3, r12}, true, ge, "ge r3 r3 r12", "ge_r3_r3_r12"},
132 {{cc, r12, r12, r0}, true, cc, "cc r12 r12 r0", "cc_r12_r12_r0"},
153 {{mi, r2, r2, r12}, true, mi, "mi r2 r2 r12", "mi_r2_r2_r12"},
155 {{cc, r5, r5, r12}, true, cc, "cc r5 r5 r12", "cc_r5_r5_r12"},
160 {{vc, r9, r9, r12}, true, vc, "vc r9 r9 r12", "vc_r9_r9_r12"},
[all …]
|
| /external/tremolo/Tremolo/ |
| D | mdctLARM.s | 61 LDMDB r2!,{r5,r6,r7,r12}
66 MOV r12,r12,ASR #9 @ r12= (*--r)>>9
68 MOV r14,r12,ASR #15
70 EORNE r12,r4, r14,ASR #31
71 STRH r12,[r0], r3
121 LDR r12,[r2],#8
126 RSB r12,r12,#0
131 MOV r12, r12,ASR #9 @ r12= (-*l)>>9
136 MOV r14,r12,ASR #15
138 EORNE r12,r4, r14,ASR #31
[all …]
|
| D | mdctARM.s | 63 LDMDB r2!,{r5,r6,r7,r12}
68 MOV r12,r12,ASR #9 @ r12= (*--r)>>9
70 MOV r14,r12,ASR #15
72 EORNE r12,r4, r14,ASR #31
73 STRH r12,[r0], r3
123 LDR r12,[r2],#8
128 RSB r12,r12,#0
133 MOV r12, r12,ASR #9 @ r12= (-*l)>>9
138 MOV r14,r12,ASR #15
140 EORNE r12,r4, r14,ASR #31
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_inter_pred_chroma_horz.s | 112 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
126 sub r12,r0,#2 @pu1_src - 2
128 add r4,r12,r2 @pu1_src_tmp2_8 = pu1_src + src_strd
157 add r4,r12,r2
159 and r0, r12, #31
161 pld [r12, r2, lsl #1]
166 vld1.u32 {q0},[r12],r11 @vector load pu1_src
168 vld1.u32 {q1},[r12],r11 @vector load pu1_src
170 vld1.u32 {q2},[r12],r11 @vector load pu1_src
172 vld1.u32 {q3},[r12],r9 @vector load pu1_src
[all …]
|
| D | ihevc_intra_pred_chroma_horz.s | 101 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
108 add r12,r0,r6 @*pu1_ref[four_nt]
118 sub r12,r12,#16 @move to 16th value pointer
122 vld1.16 {q0},[r12] @load 16 values. d1[7] will have the 1st value.
123 sub r12,r12,#16
124 vld1.16 {q5},[r12] @load 16 values. d1[7] will have the 1st value.
180 sub r12,r12,#16 @move to 16th value pointer
194 ldmfd sp!,{r4-r12,r15} @reload the registers from sp
198 ldrb lr,[r12],#1 @pu1_ref[two_nt]
199 @vld1.8 {q15},[r12] @pu1_ref[two_nt + 1 + col]
[all …]
|
| D | ihevc_inter_pred_chroma_horz_w16out.s | 110 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
128 sub r12,r0,#2 @pu1_src - 2
130 add r4,r12,r2 @pu1_src_tmp2_8 = pu1_src + src_strd
170 add r4,r12,r2
173 and r0, r12, #31
174 pld [r12, r2, lsl #1]
182 vld1.u32 {q0},[r12],r11 @vector load pu1_src
185 vld1.u32 {q1},[r12],r11 @vector load pu1_src
188 vld1.u32 {q2},[r12],r11 @vector load pu1_src
191 vld1.u32 {q3},[r12],r9 @vector load pu1_src
[all …]
|
| /external/boringssl/linux-arm/crypto/chacha/ |
| D | chacha-armv4.S | 53 ldr r12,[sp,#0] @ pull pointer to counter and nonce
78 ldmia r12,{r4,r5,r6,r7} @ load counter and nonce
94 str r12, [sp,#4*(32+1)] @ save inp
98 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
109 mov r12,r12,ror#16
112 eor r12,r12,r0,ror#16
114 add r8,r8,r12
121 mov r12,r12,ror#24
124 eor r12,r12,r0,ror#24
126 add r8,r8,r12
[all …]
|
| /external/boringssl/ios-arm/crypto/chacha/ |
| D | chacha-armv4.S | 54 ldr r12,[sp,#0] @ pull pointer to counter and nonce
79 ldmia r12,{r4,r5,r6,r7} @ load counter and nonce
95 str r12, [sp,#4*(32+1)] @ save inp
99 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
110 mov r12,r12,ror#16
113 eor r12,r12,r0,ror#16
115 add r8,r8,r12
122 mov r12,r12,ror#24
125 eor r12,r12,r0,ror#24
127 add r8,r8,r12
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MSP430/ |
| D | setcc.ll | 12 ; CHECK: bit.w r13, r12
13 ; CHECK: mov.w r2, r12
14 ; CHECK: rra.w r12
15 ; CHECK: and.w #1, r12
24 ; CHECK: bit.w r13, r12
25 ; CHECK: mov.w r2, r12
26 ; CHECK: and.w #1, r12
34 ; CHECK: cmp.w r13, r12
37 ; CHECK: mov.w #1, r12
38 ; CHECK: bic.w r13, r12
[all …]
|