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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dlivephysregs-add-pristines.mir3 # The register r23 is live on the path bb.0->bb.2->bb.3. Make sure we add
4 # an implicit use of r23 to the predicated redefinition:
5 # CHECK: $r23 = A2_tfrt killed $p0, killed $r1, implicit killed $r23
9 # r23 in this testcase to be dropped from the Redefs set, and subsequently
16 - { id: 0, offset: 0, size: 4, alignment: 4, callee-saved-register: '$r23' }
20 liveins: $r0, $r1, $r23
27 $r23 = A2_tfr killed $r1
32 liveins: $r1, $r23
36 liveins: $r23
Danti-dep-partial.mir16 liveins: $r0, $r1, $d1, $d2, $r16, $r17, $r19, $r22, $r23
17 $r2 = A2_add $r23, killed $r17
25 $r23 = S2_asr_i_r $r22, 31
27 ; The anti-dependency on r23 between the first A2_add and the
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AVR/
Dinst-fmulsu.s8 fmulsu r21, r23
9 fmulsu r23, r23
13 ; CHECK: fmulsu r21, r23 ; encoding: [0xdf,0x03]
14 ; CHECK: fmulsu r23, r23 ; encoding: [0xff,0x03]
Dinst-fmul.s8 fmul r21, r23
9 fmul r23, r23
13 ; CHECK: fmul r21, r23 ; encoding: [0x5f,0x03]
14 ; CHECK: fmul r23, r23 ; encoding: [0x7f,0x03]
Dinst-mulsu.s8 mulsu r21, r23
9 mulsu r23, r23
13 ; CHECK: mulsu r21, r23 ; encoding: [0x57,0x03]
14 ; CHECK: mulsu r23, r23 ; encoding: [0x77,0x03]
Dinst-fmuls.s8 fmuls r21, r23
9 fmuls r23, r23
13 ; CHECK: fmuls r21, r23 ; encoding: [0xd7,0x03]
14 ; CHECK: fmuls r23, r23 ; encoding: [0xf7,0x03]
/external/u-boot/include/
Dppc_asm.tmpl73 #define r23 23
171 stw r23,GPR23(r21); \
185 mfspr r23,reg2; \
194 * r21, r22 (SRR0), and r23 (SRR1).
210 stw r23,_MSR(r21); \
211 li r23,n; \
212 stw r23,TRAP(r21); \
214 copyee(r20,r23); \
215 rlwimi r20,r23,0,25,25; \
218 1: mflr r23; \
[all …]
/external/libffi/src/microblaze/
Dsysv.S51 swi r23, r1, 16 /* save for locals */
65 addik r23, r10, 0 /* save function address into r23 (callee-saved) */
94 brald r15, r23
115 lwi r23, r1, 52 /* get return size (20 for locals + 32 for arg[7]) */
122 rsubi r11, r23, 1
126 rsubi r11, r23, 2
130 rsubi r11, r23, 4
134 rsubi r11, r23, 8
171 lwi r23, r1, 16
/external/python/cpython2/Modules/_ctypes/libffi/src/microblaze/
Dsysv.S51 swi r23, r1, 16 /* save for locals */
65 addik r23, r10, 0 /* save function address into r23 (callee-saved) */
94 brald r15, r23
115 lwi r23, r1, 52 /* get return size (20 for locals + 32 for arg[7]) */
122 rsubi r11, r23, 1
126 rsubi r11, r23, 2
130 rsubi r11, r23, 4
134 rsubi r11, r23, 8
171 lwi r23, r1, 16
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dtwo-extenders.s9 if (p3) r23 = memb(##2164335510)
13 # CHECK: if (p3) r23 = memb(##2164335510)
19 if (p3.new) r23 = memb(##2164335510)
24 # CHECK: if (p3.new) r23 = memb(##2164335510) }
108 # CHECK: { r23 = #1
110 # CHECK-NEXT: memh(##4096) = r23.new }
DasmMap.s17 #CHECK: 4519d817 { if (!p3) r23 = memb(r25+#0)
18 if (!p3) r23=memb(r25)
68 #CHECK: 910bc017 { r23 = memb(r11+#0)
69 r23=memb(r11)
107 #CHECK: 38b7c013 { if (!p0) memh(r23+#0) = #19
108 if (!p0) memh(r23)=#19
170 #CHECK: a157d100 { memh(r23+#0) = r17
171 memh(r23)=r17
236 p1=cmp.eq(r23,##-1105571618)
271 p0=cmp.eq(r23,##127565957)
[all …]
Dv60-vmem.s185 #CHECK: 2b97f031 { if (!q2) vmem(r23++m1) = v17 }
187 if (!q2) vmem(r23++m1)=v17
235 #CHECK: 28f7fd3a { if (!p3) vmem(r23+#-3):nt = v26 }
237 if (!p3) vmem(r23+#-3):nt=v26
312 #CHECK: 2b17e048 v8.tmp = vmem(r23++m1) }
314 v8.tmp=vmem(r23++m1)
384 #CHECK: 29f7cd7a if (!p1) vmem(r23++#-3):nt = v1.new }
387 if(!p1)vmem(r23++#-3):nt=v1.new
402 #CHECK: 2bb7f042 if (p2) vmem(r23++m1) = v6.new }
405 if(p2)vmem(r23++m1)=v6.new
/external/linux-kselftest/tools/testing/selftests/powerpc/pmu/ebb/
Dbusy_loop.S21 std r23, 88(%r1)
67 li r23, 0x2323
68 std r23, -240(%r1)
127 cmpwi r23, 0x2323
165 li r23, 0xbe
227 ld r23, -240(%r1)
228 cmpwi r23, 0x2323
261 ld r23, 88(%r1)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Dor.ll20 ; CHECK: or r25, r23
36 ; CHECK: or r23, r19
46 ; CHECK: ori r23, 205
60 ; CHECK: or r23, r15
74 ; CHECK: ori r23, 204
Dand.ll20 ; CHECK: and r25, r23
36 ; CHECK: and r23, r19
46 ; CHECK: andi r23, 205
60 ; CHECK: and r23, r15
75 ; CHECK: andi r23, 73
Dadd.ll28 ; CHECK: adc r25, r23
51 ; CHECK: adc r23, r19
61 ; CHECK: sbci r23, 255
74 ; CHECK: adc r23, r15
88 ; CHECK: sbci r23, 255
Dsub.ll27 ; CHECK: sbc r25, r23
50 ; CHECK: sbc r23, r19
60 ; CHECK: sbci r23, 205
73 ; CHECK: sbc r23, r15
87 ; CHECK: sbci r23, 22
Deor.ll23 ; CHECK: eor r25, r23
41 ; CHECK: eor r23, r19
53 ; CHECK: eor r23, r19
65 ; CHECK: eor r23, r15
85 ; CHECK: eor r23, r31
Dxor.ll13 ; CHECK: eor r25, r23
21 ; CHECK: eor r23, r19
35 ; CHECK: eor r23, r15
/external/llvm/test/CodeGen/MIR/Hexagon/
Danti-dep-partial.mir17 liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23
18 %r2 = A2_add %r23, killed %r17
26 %r23 = S2_asr_i_r %r22, 31
28 ; The anti-dependency on r23 between the first A2_add and the
/external/llvm/test/MC/Hexagon/
DasmMap.s17 #CHECK: 4519d817 { if (!p3) r23 = memb(r25{{ *}}+{{ *}}#0)
18 if (!p3) r23=memb(r25)
68 #CHECK: 910bc017 { r23 = memb(r11{{ *}}+{{ *}}#0)
69 r23=memb(r11)
107 #CHECK: 38b7c013 { if (!p0) memh(r23{{ *}}+{{ *}}#0)=#19
108 if (!p0) memh(r23)=#19
170 #CHECK: a157d100 { memh(r23{{ *}}+{{ *}}#0) = r17
171 memh(r23)=r17
236 p1=cmp.eq(r23,##-1105571618)
271 p0=cmp.eq(r23,##127565957)
[all …]
Dv60-vmem.s185 #CHECK: 2b97f031 { if (!q2) vmem(r23++m1) = v17 }
187 if (!q2) vmem(r23++m1)=v17
235 #CHECK: 28f7fd3a { if (!p3) vmem(r23+#-3):nt = v26 }
237 if (!p3) vmem(r23+#-3):nt=v26
312 #CHECK: 2b17e048 v8.tmp = vmem(r23++m1) }
314 v8.tmp=vmem(r23++m1)
384 #CHECK: 29f7cd7a if(!p1) vmem(r23++#-3):nt = v1.new }
387 if(!p1)vmem(r23++#-3):nt=v1.new
402 #CHECK: 2bb7f042 if(p2) vmem(r23++m1) = v6.new }
405 if(p2)vmem(r23++m1)=v6.new
/external/libunwind/src/ia64/
DGinstall_cursor.S91 ld8 r23 = [r2], 2*LOC_SIZE // r23 = loc[IA64_REG_FR23]
102 and r23 = -4, r23
106 ldf.fill f23 = [r23] // f23 restored (don't touch no more)
184 ld8 r23 = [r3], (UNAT_LOC_OFF - F4_LOC_OFF) // r22 = f4_loc
198 and r23 = -4, r23
207 ldf.fill f4 = [r23] // f4 restored (don't touch no more)
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dstart.S270 andc r23,r23,r22
271 stw r23,_MSR(r21)
276 mflr r23
277 andi. r24,r23,0x3f00 /* get vector offset */
282 lwz r24,0(r23) /* virtual address of handler */
283 lwz r23,4(r23) /* where to go when done */
286 mtlr r23
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dfold-vector-zero.ll9 %l0 = phi i64 [ -2222, %bb8 ], [ %r23, %bb30 ]
27 %r23 = add i64 1, %l0
28 %r25 = icmp slt i64 %r23, 0

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