| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3128.c | 30 .refdiv = _refdiv,\
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
64 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
78 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config() local
111 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
112 fref_khz = ref_khz / refdiv; in pll_para_config()
127 div->refdiv = refdiv; in pll_para_config()
241 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
270 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
[all …]
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| D | clk_rk322x.c | 29 .refdiv = _refdiv,\
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
67 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
203 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
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| D | clk_rk3399.c | 33 u32 refdiv; member
45 .refdiv = _refdiv,\
294 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
299 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
323 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
336 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
369 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_para_config()
370 fref_khz = ref_khz / refdiv; in pll_para_config()
385 div->refdiv = refdiv; in pll_para_config()
779 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; in rk3399_ddr_set_clk()
[all …]
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| D | clk_rk3036.c | 32 .refdiv = _refdiv,\
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
69 div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
202 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| D | clk_rv1108.c | 30 .refdiv = _refdiv,\
63 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
77 refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; in rkclk_pll_get_rate()
78 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| D | clk_rk3328.c | 21 u32 refdiv; member
33 .refdiv = _refdiv,\
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
269 (div->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
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| /external/u-boot/arch/mips/mach-ath79/ar934x/ |
| D | clk.c | 31 u8 refdiv; member
144 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
153 pll_refdiv = pll_cfg->refdiv; in ar934x_pll_init()
232 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz() local
240 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_cpupll_to_hz()
247 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz() local
255 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_ddrpll_to_hz()
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| /external/u-boot/arch/arm/mach-socfpga/ |
| D | clock_manager_s10.c | 175 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
193 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_main_vco_clk_hz()
199 vco = fref / refdiv; in cm_get_main_vco_clk_hz()
206 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_per_vco_clk_hz() local
224 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_per_vco_clk_hz()
230 vco = fref / refdiv; in cm_get_per_vco_clk_hz()
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| /external/u-boot/arch/m68k/cpu/mcf532x/ |
| D | speed.c | 68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock() local
71 return (((FREF * pfdr) / refdiv) / busdiv); in get_sys_clock()
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| /external/u-boot/arch/mips/mach-ath79/ar933x/ |
| D | lowlevel_init.S | 19 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
21 ((0x1F & refdiv) << 16) | \
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| /external/u-boot/arch/mips/mach-ath79/qca953x/ |
| D | lowlevel_init.S | 14 #define MK_PLL_CONF(divint, refdiv, range, outdiv) \ argument
16 ((0x1F & refdiv) << 16) | \
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | cru_rv1108.h | 50 u32 refdiv; member
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| D | cru_rk3036.h | 61 u32 refdiv; member
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| D | cru_rk3128.h | 64 u32 refdiv; member
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| D | cru_rk322x.h | 62 u32 refdiv; member
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| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| D | sdram_rk3036.c | 344 dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); in rkdclk_init()
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