| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
21 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
25 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg8, in vpx_idct16_1d_rows_msa()
26 reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
41 DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3); in vpx_idct16_1d_rows_msa()
43 reg9 = reg1 - loc2; in vpx_idct16_1d_rows_msa()
65 DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9); in vpx_idct16_1d_rows_msa()
68 loc0 = reg9 + reg5; in vpx_idct16_1d_rows_msa()
69 reg5 = reg9 - reg5; in vpx_idct16_1d_rows_msa()
80 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
[all …]
|
| /external/elfutils/tests/ |
| D | run-dwarfcfi.sh | 47 reg9: undefined
64 reg9: undefined
81 reg9: undefined
98 reg9: undefined
115 reg9: undefined
132 reg9: undefined
|
| D | run-addrcfi.sh | 42 integer reg9 (%eflags): undefined
89 integer reg9 (%eflags): undefined
141 integer reg9 (%r9): undefined
207 integer reg9 (%r9): undefined
311 integer reg9 (r9): undefined
1333 integer reg9 (r9): undefined
2361 integer reg9 (r9): undefined
3387 integer reg9 (%r9): same_value
3464 integer reg9 (%r9): same_value
3542 integer reg9 (r9): undefined
[all …]
|
| /external/u-boot/include/ |
| D | ns16550.h | 76 UART_REG(reg9); /* 9 */
83 UART_REG(reg9); /* 9 */
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | scale_msa.cc | 767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
811 reg9 = (v8i16)__msa_dotp_u_h(vec9, const0); in ScaleRowDown34_0_Box_MSA()
823 reg9 = __msa_srar_h(reg9, shft0); in ScaleRowDown34_0_Box_MSA()
829 reg3 = reg3 * 3 + reg9; in ScaleRowDown34_0_Box_MSA()
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
905 reg9 = (v8i16)__msa_dotp_u_h(vec9, const0); in ScaleRowDown34_1_Box_MSA()
917 reg9 = __msa_srar_h(reg9, shft0); in ScaleRowDown34_1_Box_MSA()
923 reg3 += reg9; in ScaleRowDown34_1_Box_MSA()
|
| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
901 reg9 = reg3 * const_0x4A; in ARGBToUVRow_MSA()
905 reg9 += reg5 * const_0x26; in ARGBToUVRow_MSA()
917 reg7 -= reg9; in ARGBToUVRow_MSA()
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
2706 reg9 = (v4i32)__msa_ilvl_h((v8i16)zero, (v8i16)vec1); in I444ToARGBRow_MSA()
2712 reg5 -= reg9 * vec_vr; in I444ToARGBRow_MSA()
2714 reg3 -= reg9 * vec_vg; in I444ToARGBRow_MSA()
|
| /external/libyuv/files/source/ |
| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
901 reg9 = reg3 * const_0x4A; in ARGBToUVRow_MSA()
905 reg9 += reg5 * const_0x26; in ARGBToUVRow_MSA()
917 reg7 -= reg9; in ARGBToUVRow_MSA()
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
2694 reg9 = (v4i32)__msa_ilvl_h((v8i16)zero, (v8i16)vec1); in I444ToARGBRow_MSA()
2700 reg5 -= reg9 * vec_vr; in I444ToARGBRow_MSA()
2702 reg3 -= reg9 * vec_vg; in I444ToARGBRow_MSA()
|
| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 210 HANDLE_DW_OP(0x59, reg9)
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | big_alu.ll | 5 … x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) {
12 %tmp5 = extractelement <4 x float> %reg9, i32 0
17 %tmp10 = extractelement <4 x float> %reg9, i32 1
22 %tmp15 = extractelement <4 x float> %reg9, i32 2
27 %tmp20 = extractelement <4 x float> %reg9, i32 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | big_alu.ll | 5 …float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #0 {
12 %tmp5 = extractelement <4 x float> %reg9, i32 0
17 %tmp10 = extractelement <4 x float> %reg9, i32 1
22 %tmp15 = extractelement <4 x float> %reg9, i32 2
27 %tmp20 = extractelement <4 x float> %reg9, i32 3
|
| /external/elfutils/libdw/ |
| D | known-dwarf.h | 529 DWARF_ONE_KNOWN_DW_OP (reg9, DW_OP_reg9) \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/BinaryFormat/ |
| D | Dwarf.def | 533 HANDLE_DW_OP(0x59, reg9, 2, DWARF)
|