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Searched refs:reg_size (Results 1 – 25 of 60) sorted by relevance

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/external/v8/src/arm64/
Ddeoptimizer-arm64.cc28 int reg_size = reg_list.RegisterSizeInBytes(); in CopyRegListToFrame() local
29 DCHECK_EQ(temp0.SizeInBytes(), reg_size); in CopyRegListToFrame()
30 DCHECK_EQ(temp1.SizeInBytes(), reg_size); in CopyRegListToFrame()
41 masm->Ldp(temp0, temp1, MemOperand(src, i * reg_size)); in CopyRegListToFrame()
45 int offset0 = reg0.code() * reg_size; in CopyRegListToFrame()
46 int offset1 = reg1.code() * reg_size; in CopyRegListToFrame()
49 if (offset1 == offset0 + reg_size) { in CopyRegListToFrame()
64 int reg_size = restore_list.RegisterSizeInBytes(); in RestoreRegList() local
76 int offset0 = reg0.code() * reg_size; in RestoreRegList()
77 int offset1 = reg1.code() * reg_size; in RestoreRegList()
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Dassembler-arm64-inl.h956 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
957 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
958 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
959 USE(reg_size);
964 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
965 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
966 ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
967 USE(reg_size);
973 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
974 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
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Dinstructions-arm64.cc80 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, in RepeatBitsAcrossReg() argument
85 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); in RepeatBitsAcrossReg()
87 for (unsigned i = width; i < reg_size; i *= 2) { in RepeatBitsAcrossReg()
98 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; in ImmLogical() local
137 return RepeatBitsAcrossReg(reg_size, in ImmLogical()
Dmacro-assembler-arm64.cc125 unsigned reg_size = rd.SizeInBits(); in LogicalMacro() local
180 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { in LogicalMacro()
246 unsigned reg_size = rd.SizeInBits(); in Mov() local
257 if (CountClearHalfWords(~imm, reg_size) > in Mov()
258 CountClearHalfWords(imm, reg_size)) { in Mov()
270 DCHECK_EQ(reg_size % 16, 0); in Mov()
552 unsigned TurboAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) { in CountClearHalfWords() argument
553 DCHECK_EQ(reg_size % 8, 0); in CountClearHalfWords()
555 for (unsigned i = 0; i < (reg_size / 16); i++) { in CountClearHalfWords()
567 bool TurboAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) { in IsImmMovz() argument
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Ddisasm-arm64.cc232 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits in VisitLogicalImmediate() local
234 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) { in VisitLogicalImmediate()
257 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) { in IsMovzMovnImm() argument
258 DCHECK((reg_size == kXRegSizeInBits) || in IsMovzMovnImm()
259 ((reg_size == kWRegSizeInBits) && (value <= 0xFFFFFFFF))); in IsMovzMovnImm()
270 if ((reg_size == kXRegSizeInBits) && in IsMovzMovnImm()
277 if ((reg_size == kWRegSizeInBits) && (((value & 0xFFFF0000) == 0xFFFF0000) || in IsMovzMovnImm()
3508 unsigned reg_size; in SubstituteRegisterField() local
3519 reg_size = kWRegSizeInBits; in SubstituteRegisterField()
3523 reg_size = kXRegSizeInBits; in SubstituteRegisterField()
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/external/jemalloc_new/src/
Dbin.c8 #define BIN_INFO_bin_yes(reg_size, slab_size, nregs) \ argument
9 {reg_size, slab_size, nregs, BITMAP_INFO_INITIALIZER(nregs)},
10 #define BIN_INFO_bin_no(reg_size, slab_size, nregs) argument
Dandroid_je_mallinfo.c41 total_bytes += bin_infos[j].reg_size * bin->stats.curregs; in accumulate_small_allocs()
107 mi.ordblks = bin_infos[bidx].reg_size * bin->stats.curregs; in je_mallinfo_bin_info()
/external/mesa3d/src/intel/compiler/
Dbrw_fs_reg_allocate.cpp758 const unsigned reg_size = dst.component_size(bld.dispatch_width()) / in emit_unspill() local
760 assert(count % reg_size == 0); in emit_unspill()
762 for (unsigned i = 0; i < count / reg_size; i++) { in emit_unspill()
783 dst.offset += reg_size * REG_SIZE; in emit_unspill()
784 spill_offset += reg_size * REG_SIZE; in emit_unspill()
792 const unsigned reg_size = src.component_size(bld.dispatch_width()) / in emit_spill() local
794 assert(count % reg_size == 0); in emit_spill()
796 for (unsigned i = 0; i < count / reg_size; i++) { in emit_spill()
799 src.offset += reg_size * REG_SIZE; in emit_spill()
800 spill_inst->offset = spill_offset + i * reg_size * REG_SIZE; in emit_spill()
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Dbrw_ir_vec4.h429 const unsigned reg_size = in regs_read() local
431 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
432 reg_size); in regs_read()
Dbrw_ir_fs.h441 const unsigned reg_size = in regs_read() local
443 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + in regs_read()
446 reg_size); in regs_read()
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc332 uint64_t Simulator::AddWithCarry(unsigned reg_size, in AddWithCarry() argument
338 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize)); in AddWithCarry()
340 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt; in AddWithCarry()
341 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; in AddWithCarry()
342 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask; in AddWithCarry()
349 ReadNzcv().SetN(CalcNFlag(result, reg_size)); in AddWithCarry()
371 int64_t Simulator::ShiftOperand(unsigned reg_size, in ShiftOperand() argument
375 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in ShiftOperand()
382 if (reg_size == kXRegSize) { in ShiftOperand()
398 uvalue |= ~UINT64_C(0) << (reg_size - amount); in ShiftOperand()
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Dinstructions-aarch64.cc33 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, in RepeatBitsAcrossReg() argument
38 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); in RepeatBitsAcrossReg()
40 for (unsigned i = width; i < reg_size; i *= 2) { in RepeatBitsAcrossReg()
110 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; in GetImmLogical() local
149 return RepeatBitsAcrossReg(reg_size, in GetImmLogical()
Dmacro-assembler-aarch64.cc444 unsigned reg_size = rd.GetSizeInBits(); in MoveImmediateHelper() local
455 if (CountClearHalfWords(~imm, reg_size) > in MoveImmediateHelper()
456 CountClearHalfWords(imm, reg_size)) { in MoveImmediateHelper()
472 VIXL_ASSERT((reg_size % 16) == 0); in MoveImmediateHelper()
474 for (unsigned i = 0; i < (reg_size / 16); i++) { in MoveImmediateHelper()
512 int reg_size = dst.GetSizeInBits(); in OneInstrMoveImmediateHelper() local
514 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()
521 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()
528 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) { in OneInstrMoveImmediateHelper()
813 unsigned reg_size = rd.GetSizeInBits(); in LogicalMacro() local
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Dassembler-aarch64.h813 unsigned reg_size = rd.GetSizeInBits(); in lsl() local
814 VIXL_ASSERT(shift < reg_size); in lsl()
815 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1); in lsl()
3655 static Instr ImmS(unsigned imms, unsigned reg_size) { in ImmS() argument
3656 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) || in ImmS()
3657 ((reg_size == kWRegSize) && IsUint5(imms))); in ImmS()
3658 USE(reg_size); in ImmS()
3662 static Instr ImmR(unsigned immr, unsigned reg_size) { in ImmR() argument
3663 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(immr)) || in ImmR()
3664 ((reg_size == kWRegSize) && IsUint5(immr))); in ImmR()
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/external/jemalloc/src/
Dandroid_je_mallinfo.c37 mi.uordblks += arena_bin_info[j].reg_size * bin->stats.curregs; in je_mallinfo()
73 mi.fsmblks += arena_bin_info[j].reg_size * bin->stats.curregs; in __mallinfo_arena_info()
92 mi.ordblks = arena_bin_info[bidx].reg_size * bin->stats.curregs; in __mallinfo_bin_info()
Dstats.c69 size_t reg_size, run_size, curregs; in stats_arena_bins_print() local
85 CTL_M2_GET("arenas.bin.0.size", j, &reg_size, size_t); in stats_arena_bins_print()
159 reg_size, j, curregs * reg_size, nmalloc, in stats_arena_bins_print()
169 reg_size, j, curregs * reg_size, nmalloc, in stats_arena_bins_print()
/external/jemalloc_new/test/unit/
Dslab.c17 (bin_info->reg_size * regind)); in TEST_BEGIN()
21 bin_info->reg_size); in TEST_BEGIN()
Djunk.c22 for (i = 0; i < bin_info->reg_size; i++) { in arena_dalloc_junk_small_intercept()
25 i, bin_info->reg_size); in arena_dalloc_junk_small_intercept()
/external/u-boot/arch/arm/cpu/armv7/
Dmpu_v7r.c73 if (rgn->reg_size) in mpu_config()
74 val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION; in mpu_config()
/external/jemalloc_new/include/jemalloc/internal/
Dsize_classes.sh61 reg_size=$((${grp} + ${delta}*${ndelta}))
75 try_nregs=$((${try_slab_size} / ${reg_size}))
82 try_nregs=$((${try_slab_size} / ${reg_size}))
83 if [ ${perfect_slab_size} -eq $((${perfect_nregs} * ${reg_size})) ] ; then
/external/jemalloc/test/unit/
Djunk.c31 for (i = 0; i < bin_info->reg_size; i++) { in arena_dalloc_junk_small_intercept()
34 i, bin_info->reg_size); in arena_dalloc_junk_small_intercept()
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h257 int reg_size,
265 int reg_size,
Dtest-utils-aarch64.cc320 int reg_size, in PopulateRegisterArray() argument
329 r[i] = Register(n, reg_size); in PopulateRegisterArray()
351 int reg_size, in PopulateFPRegisterArray() argument
360 v[i] = FPRegister(n, reg_size); in PopulateFPRegisterArray()
/external/vixl/src/
Dutils-vixl.cc191 unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size) { in CountClearHalfWords() argument
192 VIXL_ASSERT((reg_size % 8) == 0); in CountClearHalfWords()
194 for (unsigned i = 0; i < (reg_size / 16); i++) { in CountClearHalfWords()
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_compiler.c130 size_t reg_size; member
260 for (int idx = 0; idx < file->reg_size; ++idx) { in sort_registers()
306 for (int idx = 0; idx < file->reg_size; ++idx) in assign_temporaries_to_native()
516 c->file[x].reg_size = c->info.file_max[x] + 1; in etna_allocate_decls()
518 for (int sub = 0; sub < c->file[x].reg_size; ++sub) { in etna_allocate_decls()
1873 for (int idx = 0; idx < c->file[file].reg_size; ++idx) { in find_decl_by_semantic()
1955 for (int idx = 0; idx < file->reg_size; ++idx) { in assign_uniforms()
1974 c->imm_base = c->file[TGSI_FILE_CONSTANT].reg_size * 4; in assign_constants_and_immediates()
1989 for (int idx = 0; idx < c->file[TGSI_FILE_SAMPLER].reg_size; ++idx) { in assign_texture_units()
2048 for (int idx = 0; idx < c->file[TGSI_FILE_INPUT].reg_size; ++idx) { in permute_ps_inputs()
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