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Searched refs:rors (Results 1 – 25 of 26) sorted by relevance

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/external/capstone/suite/MC/ARM/
Dthumb2-narrow-dp.ll.cs266 0x72,0xfa,0x01,0xf3 = rors.w r3, r2, r1
267 0xc8,0x41 = rors r0, r1
268 0x70,0xfa,0x01,0xf1 = rors.w r1, r0, r1
269 0x72,0xfa,0x01,0xf2 = rors.w r2, r2, r1
270 0x71,0xfa,0x02,0xf2 = rors.w r2, r1, r2
272 0xcf,0x41 = rors r7, r1
273 0x71,0xfa,0x08,0xf8 = rors.w r8, r1, r8
274 0x78,0xfa,0x01,0xf8 = rors.w r8, r8, r1
275 0x78,0xfa,0x06,0xf6 = rors.w r6, r8, r6
276 0x76,0xfa,0x08,0xf6 = rors.w r6, r6, r8
Dbasic-thumb2-instructions.s.cs462 0x5f,0xea,0x72,0x16 = rors.w r6, r2, #5
466 0xec,0x41 = rors r4, r5
468 0x74,0xfa,0x08,0xf4 = rors.w r4, r4, r8
625 0x5f,0xea,0xf3,0x78 = rors.w r8, r3, #31
626 0x5f,0xea,0x73,0x02 = rors.w r2, r3, #1
628 0x5f,0xea,0xfc,0x32 = rors.w r2, r12, #15
630 0x5f,0xea,0xb8,0x08 = rors.w r8, r8, #2
631 0x5f,0xea,0x77,0x17 = rors.w r7, r7, #5
635 0x74,0xfa,0x08,0xf3 = rors.w r3, r4, r8
Dbasic-thumb-instructions.s.cs94 0xfa,0x41 = rors r2, r7
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dthumb_rewrites.s89 rors r0, r0, r1
90 @ CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
Dthumb2-narrow-dp.ll666 // CHECK: rors.w r3, r2, r1 @ encoding: [0x72,0xfa,0x01,0xf3]
667 // CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
668 // CHECK: rors.w r1, r0, r1 @ encoding: [0x70,0xfa,0x01,0xf1]
669 // CHECK: rors.w r2, r2, r1 @ encoding: [0x72,0xfa,0x01,0xf2]
670 // CHECK: rors.w r2, r1, r2 @ encoding: [0x71,0xfa,0x02,0xf2]
672 // CHECK: rors r7, r1 @ encoding: [0xcf,0x41]
673 // CHECK: rors.w r8, r1, r8 @ encoding: [0x71,0xfa,0x08,0xf8]
674 // CHECK: rors.w r8, r8, r1 @ encoding: [0x78,0xfa,0x01,0xf8]
675 // CHECK: rors.w r6, r8, r6 @ encoding: [0x78,0xfa,0x06,0xf6]
676 // CHECK: rors.w r6, r6, r8 @ encoding: [0x76,0xfa,0x08,0xf6]
Dbasic-thumb2-instructions.s1531 @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16]
1532 @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16]
1539 @ CHECK: rors r4, r5 @ encoding: [0xec,0x41]
1540 @ CHECK: rors.w r4, r4, r5 @ encoding: [0x74,0xfa,0x05,0xf4]
1542 @ CHECK: rors.w r4, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf4]
2031 rors r8, r3, #31
2032 rors.w r2, r3, #1
2034 rors r2, r12, #15
2037 rors r8, #2
2038 rors.w r7, #5
[all …]
Dbasic-thumb-instructions.s486 rors r2, r7
488 @ CHECK: rors r2, r7 @ encoding: [0xfa,0x41]
/external/llvm/test/MC/ARM/
Dthumb_rewrites.s89 rors r0, r0, r1
90 @ CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
Dthumb2-narrow-dp.ll666 // CHECK: rors.w r3, r2, r1 @ encoding: [0x72,0xfa,0x01,0xf3]
667 // CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
668 // CHECK: rors.w r1, r0, r1 @ encoding: [0x70,0xfa,0x01,0xf1]
669 // CHECK: rors.w r2, r2, r1 @ encoding: [0x72,0xfa,0x01,0xf2]
670 // CHECK: rors.w r2, r1, r2 @ encoding: [0x71,0xfa,0x02,0xf2]
672 // CHECK: rors r7, r1 @ encoding: [0xcf,0x41]
673 // CHECK: rors.w r8, r1, r8 @ encoding: [0x71,0xfa,0x08,0xf8]
674 // CHECK: rors.w r8, r8, r1 @ encoding: [0x78,0xfa,0x01,0xf8]
675 // CHECK: rors.w r6, r8, r6 @ encoding: [0x78,0xfa,0x06,0xf6]
676 // CHECK: rors.w r6, r6, r8 @ encoding: [0x76,0xfa,0x08,0xf6]
Dbasic-thumb2-instructions.s1488 @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16]
1492 @ CHECK: rors r4, r5 @ encoding: [0xec,0x41]
1494 @ CHECK: rors.w r4, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf4]
1983 rors r8, r3, #31
1984 rors.w r2, r3, #1
1986 rors r2, r12, #15
1989 rors r8, #2
1990 rors.w r7, #5
1994 @ CHECK: rors.w r8, r3, #31 @ encoding: [0x5f,0xea,0xf3,0x78]
1995 @ CHECK: rors.w r2, r3, #1 @ encoding: [0x5f,0xea,0x73,0x02]
[all …]
Dbasic-thumb-instructions.s486 rors r2, r7
488 @ CHECK: rors r2, r7 @ encoding: [0xfa,0x41]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-thumb-instructions.s435 rors r2, r7
437 @ CHECK: rors r2, r7 @ encoding: [0xfa,0x41]
Dbasic-thumb2-instructions.s1556 rors r8, r3, #31
1557 rors.w r2, r3, #1
1559 rors r2, r12, #15
1562 rors r8, #2
1563 rors.w r7, #5
1567 @ CHECK: rors.w r8, r3, #31 @ encoding: [0x5f,0xea,0xf3,0x78]
1568 @ CHECK: rors.w r2, r3, #1 @ encoding: [0x5f,0xea,0x73,0x02]
1570 @ CHECK: rors.w r2, r12, #15 @ encoding: [0x5f,0xea,0xfc,0x32]
1573 @ CHECK: rors.w r8, r8, #2 @ encoding: [0x5f,0xea,0xb8,0x08]
1574 @ CHECK: rors.w r7, r7, #5 @ encoding: [0x5f,0xea,0x77,0x17]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt356 # CHECK: rors r2, r7
Dthumb2.txt1495 # CHECK: rors.w r8, r3, #31
1496 # CHECK: rors.w r2, r3, #1
1498 # CHECK: rors.w r2, r12, #15
1501 # CHECK: rors.w r8, r8, #2
1502 # CHECK: rors.w r7, r7, #5
1522 # CHECK: rors.w r3, r4, r8
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb1.txt347 # CHECK: rors r2, r7
Dthumb2.txt1356 # CHECK: rors.w r8, r3, #31
1357 # CHECK: rors.w r2, r3, #1
1359 # CHECK: rors.w r2, r12, #15
1362 # CHECK: rors.w r8, r8, #2
1363 # CHECK: rors.w r7, r7, #5
1383 # CHECK: rors.w r3, r4, r8
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt356 # CHECK: rors r2, r7
Dthumb2.txt1495 # CHECK: rors.w r8, r3, #31
1496 # CHECK: rors.w r2, r3, #1
1498 # CHECK: rors.w r2, r12, #15
1501 # CHECK: rors.w r8, r8, #2
1502 # CHECK: rors.w r7, r7, #5
1522 # CHECK: rors.w r3, r4, r8
/external/vixl/src/aarch32/
Dassembler-aarch32.h2902 void rors(Condition cond,
2907 void rors(Register rd, Register rm, const Operand& operand) { in rors() function
2908 rors(al, Best, rd, rm, operand); in rors()
2910 void rors(Condition cond, Register rd, Register rm, const Operand& operand) { in rors() function
2911 rors(cond, Best, rd, rm, operand); in rors()
2913 void rors(EncodingSize size, in rors() function
2917 rors(al, size, rd, rm, operand); in rors()
Ddisasm-aarch32.h1022 void rors(Condition cond,
Ddisasm-aarch32.cc2302 void Disassembler::rors(Condition cond, in rors() function in vixl::aarch32::Disassembler
7496 rors(Condition::None(), in DecodeT32()
19001 rors(CurrentCond(), in DecodeT32()
20935 rors(Condition::None(), in DecodeT32()
20942 rors(CurrentCond(), in DecodeT32()
59196 rors(condition, Best, Register(rd), Register(rm), amount); in DecodeA32()
59530 rors(condition, in DecodeA32()
Dassembler-aarch32.cc8985 void Assembler::rors(Condition cond, in rors() function in vixl::aarch32::Assembler
9040 Delegate(kRors, &Assembler::rors, cond, size, rd, rm, operand); in rors()
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-operand-rm-a32.cc85 M(rors)
Dtest-assembler-cond-rd-rn-operand-rm-t32.cc85 M(rors)

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