| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 589 0x61,0x00,0xb0,0xe1 = rrxs r0, r1
590 0x6f,0xd0,0xb0,0xe1 = rrxs sp, pc
591 0x6e,0xf0,0xb0,0xe1 = rrxs pc, lr
592 0x6d,0xe0,0xb0,0xe1 = rrxs lr, sp
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| D | basic-thumb2-instructions.s.cs | 637 0x5f,0xea,0x32,0x01 = rrxs r1, r2
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-t32.cc | 58 M(rrxs)
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| D | test-assembler-cond-rd-rn-a32.cc | 58 M(rrxs)
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2157 rrxs r0, r1
2158 rrxs sp, pc
2159 rrxs pc, lr
2160 rrxs lr, sp
2162 @CHECK: rrxs r0, r1 @ encoding: [0x61,0x00,0xb0,0xe1]
2163 @CHECK: rrxs sp, pc @ encoding: [0x6f,0xd0,0xb0,0xe1]
2164 @CHECK: rrxs pc, lr @ encoding: [0x6e,0xf0,0xb0,0xe1]
2165 @CHECK: rrxs lr, sp @ encoding: [0x6d,0xe0,0xb0,0xe1]
|
| D | basic-thumb2-instructions.s | 2021 rrxs r1, r2
2027 @ CHECK: rrxs r1, r2 @ encoding: [0x5f,0xea,0x32,0x01]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2159 rrxs r0, r1
2160 rrxs sp, pc
2161 rrxs pc, lr
2162 rrxs lr, sp
2164 @CHECK: rrxs r0, r1 @ encoding: [0x61,0x00,0xb0,0xe1]
2165 @CHECK: rrxs sp, pc @ encoding: [0x6f,0xd0,0xb0,0xe1]
2166 @CHECK: rrxs pc, lr @ encoding: [0x6e,0xf0,0xb0,0xe1]
2167 @CHECK: rrxs lr, sp @ encoding: [0x6d,0xe0,0xb0,0xe1]
|
| D | basic-thumb2-instructions.s | 2069 rrxs r1, r2
2075 @ CHECK: rrxs r1, r2 @ encoding: [0x5f,0xea,0x32,0x01]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1404 # CHECK: rrxs r0, r1
1405 # CHECK: rrxs sp, pc
1406 # CHECK: rrxs pc, lr
1407 # CHECK: rrxs lr, sp
|
| D | thumb2.txt | 1533 # CHECK: rrxs r1, r2
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1404 # CHECK: rrxs r0, r1
1405 # CHECK: rrxs sp, pc
1406 # CHECK: rrxs pc, lr
1407 # CHECK: rrxs lr, sp
|
| D | thumb2.txt | 1533 # CHECK: rrxs r1, r2
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1594 rrxs r1, r2
1600 @ CHECK: rrxs r1, r2 @ encoding: [0x5f,0xea,0x32,0x01]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2923 void rrxs(Condition cond, Register rd, Register rm);
2924 void rrxs(Register rd, Register rm) { rrxs(al, rd, rm); } in rrxs() function
|
| D | disasm-aarch32.h | 1030 void rrxs(Condition cond, Register rd, Register rm);
|
| D | disasm-aarch32.cc | 2326 void Disassembler::rrxs(Condition cond, Register rd, Register rm) { in rrxs() function in vixl::aarch32::Disassembler
18883 rrxs(CurrentCond(), Register(rd), Register(rm)); in DecodeT32()
59121 rrxs(condition, Register(rd), Register(rm)); in DecodeA32()
|
| D | assembler-aarch32.cc | 9064 void Assembler::rrxs(Condition cond, Register rd, Register rm) { in rrxs() function in vixl::aarch32::Assembler
9082 Delegate(kRrxs, &Assembler::rrxs, cond, rd, rm); in rrxs()
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| D | macro-assembler-aarch32.h | 3191 rrxs(cond, rd, rm); in Rrxs()
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1394 # CHECK: rrxs r1, r2
|