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Searched refs:s_and_saveexec_b64 (Results 1 – 25 of 56) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dsetcc-sext.ll5 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
27 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
49 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
71 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
93 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
115 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
137 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
159 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
181 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
203 ; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
[all …]
Dcollapse-endcf.ll4 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
36 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
39 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
77 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
80 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
121 ; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
127 ; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
140 ; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_THEN:s\[[0-9:]+\]]]
181 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
Dsi-lower-control-flow-kill.ll4 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]],
20 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]],
46 ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]],
Dvalu-i1.ll12 ; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc
20 ; SI: s_and_saveexec_b64
67 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
93 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
121 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
156 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
198 ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
214 ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
Di1-copy-phi.ll6 ; SI: s_and_saveexec_b64
9 ; SI: s_and_saveexec_b64
Dsi-lower-control-flow-unreachable-block.ll5 ; GCN: s_and_saveexec_b64
31 ; GCN: s_and_saveexec_b64
Dhoist-cond.ll5 ; using another v_cmp + v_cndmask, but used directly in s_and_saveexec_b64.
11 ; CHECK: s_and_saveexec_b64 s[{{[[0-9]+:[0-9]+}}], [[COND]]
Dcgp-addressing-modes.ll45 ; GCN: s_and_saveexec_b64
73 ; GCN: s_and_saveexec_b64
101 ; GCN: s_and_saveexec_b64
134 ; GCN: s_and_saveexec_b64
172 ; GCN: s_and_saveexec_b64
212 ; GCN: s_and_saveexec_b64
244 ; GCN: s_and_saveexec_b64
275 ; GCN: s_and_saveexec_b64
304 ; GCN: s_and_saveexec_b64
335 ; GCN: s_and_saveexec_b64
[all …]
Duniform-loop-inside-nonuniform.ll7 ; CHECK: s_and_saveexec_b64
36 ; CHECK: s_and_saveexec_b64
Dsi-annotate-cfg-loop-assert.ll4 ; CHECK s_and_saveexec_b64
Dbranch-condition-and.ll16 ; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]]
Dsi-annotate-cf-unreachable.ll11 ; GCN: s_and_saveexec_b64
Dindirect-addressing-si.ll124 ; GCN: s_and_saveexec_b64 vcc, vcc
251 ; GCN: s_and_saveexec_b64 vcc, vcc
324 ; GCN: s_and_saveexec_b64 vcc, vcc
346 ; GCN: s_and_saveexec_b64 vcc, vcc
397 ; GCN: s_and_saveexec_b64 vcc, vcc
417 ; GCN: s_and_saveexec_b64 vcc, vcc
Dsubreg-coalescer-undef-use.ll13 ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
/external/llvm/test/CodeGen/AMDGPU/
Dcgp-addressing-modes.ll42 ; GCN: s_and_saveexec_b64
69 ; GCN: s_and_saveexec_b64
96 ; GCN: s_and_saveexec_b64
128 ; GCN: s_and_saveexec_b64
165 ; GCN: s_and_saveexec_b64
197 ; GCN: s_and_saveexec_b64
233 ; GCN: s_and_saveexec_b64
262 ; GCN: s_and_saveexec_b64
293 ; GCN: s_and_saveexec_b64
325 ; GCN: s_and_saveexec_b64
[all …]
Di1-copy-phi.ll6 ; SI: s_and_saveexec_b64
10 ; SI: s_and_saveexec_b64
Dsi-lower-control-flow-unreachable-block.ll5 ; GCN: s_and_saveexec_b64
30 ; GCN: s_and_saveexec_b64
Duniform-loop-inside-nonuniform.ll7 ; CHECK: s_and_saveexec_b64
34 ;CHECK: s_and_saveexec_b64
Dvalu-i1.ll47 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
73 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
116 ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
132 ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
Dsi-annotate-cfg-loop-assert.ll4 ; CHECK s_and_saveexec_b64
Dsubreg-coalescer-undef-use.ll12 ; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
/external/swiftshader/third_party/llvm-7.0/llvm/test/Object/AMDGPU/
Dobjdump.s19 s_and_saveexec_b64 s[0:1], vcc
33 s_and_saveexec_b64 s[0:1], vcc
/external/llvm/test/Object/AMDGPU/
Dobjdump.s17 s_and_saveexec_b64 s[0:1], vcc
30 s_and_saveexec_b64 s[0:1], vcc
/external/llvm/test/MC/AMDGPU/
Dsop1.s179 s_and_saveexec_b64 s[2:3], s[4:5] label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsop1.s182 s_and_saveexec_b64 s[2:3], s[4:5] label

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