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Searched refs:s_lshl_b32 (Results 1 – 25 of 40) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dlshl64-to-32.ll4 ; GCN: s_lshl_b32
15 ; GCN: s_lshl_b32
27 ; GCN-NOT: s_lshl_b32
38 ; GCN-NOT: s_lshl_b32
Dshl.v2i16.ll17 ; VI: s_lshl_b32
18 ; VI: s_lshl_b32
19 ; VI: s_lshl_b32
28 ; CI: s_lshl_b32
29 ; CI: s_lshl_b32
30 ; CI: s_lshl_b32
Dframe-index-amdgiz.ll22 ; CHECK: s_lshl_b32 s0, s0, 2
24 ; CHECK: s_lshl_b32 s0, s1, 2
Dinsert_vector_elt.ll208 ; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
230 ; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
231 ; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]]
252 ; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
253 ; VI: s_lshl_b32 [[SHIFTED_MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]]
269 ; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
346 ; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}}
360 ; FIXME: Should be able to manipulate m0 directly instead of s_lshl_b32 + copy to m0
Dshl_add_constant.ll58 ; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
73 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
Dinsert_vector_elt.v2i16.ll44 ; CI: s_lshl_b32 [[ELT1:s[0-9]+]], [[SHR]], 16
119 ; CI-DAG: s_lshl_b32 [[VEC_HI:s[0-9]+]], [[SHR]], 16
168 ; CIVI: s_lshl_b32 [[ELT1:s[0-9]+]], [[ELT1_LOAD]], 16
416 ; GCN-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 4
417 ; GCN-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]]
432 ; GCN-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 4
433 ; GCN-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]]
535 ; VI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
539 ; CI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
589 ; VI: s_lshl_b32 [[VAL_HI:s[0-9]+]], [[VAL]], 16
[all …]
Dextract_vector_elt-i8.ll140 ; VI-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
153 ; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
168 ; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
185 ; VI: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 3
Daddrspacecast.ll21 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
61 ; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16
172 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
Dextract_vector_elt-i16.ll25 ; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 4
114 ; GCN-DAG: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 4
Dbfe-patterns.ll67 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
143 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
Dextract_vector_elt-f16.ll24 ; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 4
86 ; GCN-DAG: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 4
Dsext-in-reg.ll528 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15
547 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14
608 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14{{$}}
625 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 8{{$}}
642 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1{{$}}
Dand.ll232 ; SI: s_lshl_b32 [[A]], [[A]], 1
233 ; SI: s_lshl_b32 [[B]], [[B]], 1
378 ; SI: s_lshl_b32 [[A]], [[A]], 1{{$}}
Dtrunc.ll26 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
Dlshr.v2i16.ll17 ; CIVI-DAG: s_lshl_b32
Dashr.v2i16.ll21 ; CIVI-DAG: s_lshl_b32
/external/llvm/test/CodeGen/AMDGPU/
Dshl_add_constant.ll59 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
75 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
Dlshl.ll4 ;CHECK: s_lshl_b32 s{{[0-9]}}, s{{[0-9]}}, 1
Dtrunc.ll24 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
Dand.ll220 ; SI: s_lshl_b32 [[A]], [[A]], 1
221 ; SI: s_lshl_b32 [[B]], [[B]], 1
342 ; SI: s_lshl_b32 [[A]], [[A]], 1{{$}}
Dindirect-addressing-si.ll460 ; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]]
476 ; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]]
/external/llvm/test/MC/AMDGPU/
Dsop2.s107 s_lshl_b32 s2, s4, s6 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsop2.s113 s_lshl_b32 s2, s4, s6 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt51 # VI: s_lshl_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8e]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt51 # VI: s_lshl_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8e]

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