Home
last modified time | relevance | path

Searched refs:s_or_b64 (Results 1 – 25 of 63) sorted by relevance

123

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dendcf-loop-header.ll4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
10 ; CHECK: s_or_b64 exec, exec
13 ; CHECK-NOT: s_or_b64 exec, exec
Dmultilevel-break.ll32 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVE_BREAK]]
35 ; GCN-NEXT: s_or_b64 [[OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[MASKED_SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
43 ; GCN-NEXT: s_or_b64 exec, exec, [[OR_BREAK]]
45 ; GCN-NEXT: s_or_b64 [[OUTER_OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[MASKED2_SAVE_BREAK]], s{{\[[0-9]+:[0-…
84 ; GCN: s_or_b64 [[BREAK_REG]], exec, [[BREAK_REG]]
Dloop_exit_with_xor.ll11 ; GCN: s_or_b64 [[REG3:[^ ,]*]], [[REG2]],
41 ; GCN: s_or_b64 [[REG2:[^ ,]*]], [[REG1]],
65 ; GCN: s_or_b64 [[REG3:[^ ,]*]], [[REG2]],
Dcollapse-endcf.ll44 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
132 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
186 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
215 ; GCN-NOT: s_or_b64 exec, exec
217 ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
221 ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
Dsi-annotate-cf.ll8 ; SI: s_or_b64
30 ; FIXME: This could be folded into the s_or_b64 instruction
36 ; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], vcc, [[ZERO]]
Dselect-opt.ll74 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
91 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
107 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
123 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
Dcgp-addressing-modes.ll49 ; GCN: s_or_b64 exec
77 ; GCN: s_or_b64 exec
105 ; GCN: s_or_b64 exec
277 ; GCN: s_or_b64 exec, exec
306 ; GCN: s_or_b64 exec, exec
339 ; GCN: s_or_b64 exec, exec
371 ; GCN: s_or_b64 exec, exec
402 ; GCN: s_or_b64 exec, exec
432 ; GCN: s_or_b64 exec, exec
470 ; GCN: s_or_b64 exec, exec
Dsi-annotate-cfg-loop-assert.ll6 ; CHECK s_or_b64 exec, exec
Dor.ll81 ; SI: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
156 ; SI: s_or_b64
252 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], vcc
265 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
Dvalu-i1.ll221 ; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
225 ; SI-NEXT: s_or_b64 exec, exec, [[ORNEG3]]
228 ; SI-NEXT: s_or_b64 [[COND_STATE]], [[MASKED_ORNEG3]], [[MOVED_TMP]]
Drotl.i64.ll8 ; BOTH: s_or_b64
Dsubreg-coalescer-undef-use.ll20 ; CHECK: s_or_b64 exec, exec, s[2:3]
Dcontrol-flow-fastregalloc.ll68 ; GCN: s_or_b64 exec, exec, s{{\[}}[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]{{\]}}
145 ; GCN: s_or_b64 exec, exec, s{{\[}}[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]{{\]}}
263 ; GCN: s_or_b64 exec, exec, s{{\[}}[[S_RELOAD_SAVEEXEC_LO]]:[[S_RELOAD_SAVEEXEC_HI]]{{\]}}
Dcontrol-flow-optnone.ll17 ; GCN: s_or_b64 exec, exec
/external/llvm/test/CodeGen/AMDGPU/
Dendcf-loop-header.ll4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
10 ; CHECK: s_or_b64 exec, exec
13 ; CHECK-NOT: s_or_b64 exec, exec
Dvalu-i1.ll55 ; SI: s_or_b64 exec, exec, [[BR_SREG]]
139 ; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
142 ; SI: s_or_b64 exec, exec, [[ORNEG2]]
143 ; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
148 ; SI: s_or_b64 exec, exec, [[COND_STATE]]
Dcgp-addressing-modes.ll45 ; GCN: s_or_b64 exec
72 ; GCN: s_or_b64 exec
99 ; GCN: s_or_b64 exec
235 ; GCN: s_or_b64 exec, exec
264 ; GCN: s_or_b64 exec, exec
297 ; GCN: s_or_b64 exec, exec
329 ; GCN: s_or_b64 exec, exec
360 ; GCN: s_or_b64 exec, exec
390 ; GCN: s_or_b64 exec, exec
428 ; GCN: s_or_b64 exec, exec
Dsi-lower-control-flow-unreachable-block.ll9 ; GCN: s_or_b64 exec, exec
34 ; GCN: s_or_b64 exec, exec
Dsi-annotate-cf.ll8 ; SI: s_or_b64
30 ; FIXME: This could be folded into the s_or_b64 instruction
36 ; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], vcc, [[ZERO]]
Dsi-annotate-cfg-loop-assert.ll6 ; CHECK s_or_b64 exec, exec
Dor.ll87 ; SI: s_or_b64
158 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
171 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
Drotl.i64.ll8 ; BOTH: s_or_b64
Dsubreg-coalescer-undef-use.ll18 ; CHECK: s_or_b64 exec, exec, s[2:3]
/external/llvm/test/MC/AMDGPU/
Dsop2.s55 s_or_b64 s[2:3], s[4:5], s[6:7] label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsop2.s61 s_or_b64 s[2:3], s[4:5], s[6:7] label

123