| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 207 define i32 @sasx(i32 %a, i32 %b) nounwind {
208 ; CHECK-LABEL: sasx
209 ; CHECK: sasx r0, r0, r1
210 %tmp = call i32 @llvm.arm.sasx(i32 %a, i32 %b)
451 declare i32 @llvm.arm.sasx(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 95 M(sasx) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 94 M(sasx) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 659 0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7
662 0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7
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| D | basic-arm-instructions.s.cs | 597 0x30,0x9f,0x1c,0xe6 = sasx r9, r12, r0
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1663 sasx r9, r2, r7
1667 @ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9]
1670 @ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9]
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| D | basic-arm-instructions.s | 1442 sasx r9, r12, r0
1445 @ CHECK: sasx r9, r12, r0 @ encoding: [0x30,0x9f,0x1c,0xe6]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2146 sasx r9, r2, r7
2150 @ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9]
2153 @ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9]
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| D | basic-arm-instructions.s | 2186 sasx r9, r12, r0
2189 @ CHECK: sasx r9, r12, r0 @ encoding: [0x30,0x9f,0x1c,0xe6]
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2098 sasx r9, r2, r7
2102 @ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9]
2105 @ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9]
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| D | basic-arm-instructions.s | 2184 sasx r9, r12, r0
2187 @ CHECK: sasx r9, r12, r0 @ encoding: [0x30,0x9f,0x1c,0xe6]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2978 void sasx(Condition cond, Register rd, Register rn, Register rm);
2979 void sasx(Register rd, Register rn, Register rm) { sasx(al, rd, rn, rm); } in sasx() function
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| D | disasm-aarch32.h | 1052 void sasx(Condition cond, Register rd, Register rn, Register rm);
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1274 # CHECK: sasx r9, r12, r0
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| D | thumb2.txt | 1458 # CHECK: sasx r9, r2, r7
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1597 # CHECK: sasx r9, r2, r7
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| D | basic-arm-instructions.txt | 1431 # CHECK: sasx r9, r12, r0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1431 # CHECK: sasx r9, r12, r0
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| D | thumb2.txt | 1597 # CHECK: sasx r9, r2, r7
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3188 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
4975 def : MnemonicAlias<"saddsubx", "sasx">;
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| D | ARMInstrThumb2.td | 1955 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3734 def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>;
5985 def : MnemonicAlias<"saddsubx", "sasx">;
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| D | ARMInstrThumb2.td | 2228 def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3589 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
5685 def : MnemonicAlias<"saddsubx", "sasx">;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1315 Mnemonic = "sasx"; // "saddsubx"
7750 "\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\003sbc\004sbfx\004sdiv"
8614 …{ 809 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feat…
8615 …{ 809 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_Co…
|