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Searched refs:sdram_params (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/ram/rockchip/
Dsdram_rk3288.c240 struct rk3288_sdram_params *sdram_params, in pctl_cfg() argument
245 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; in pctl_cfg()
246 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
247 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
248 switch (sdram_params->base.dramtype) { in pctl_cfg()
250 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
252 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
263 sdram_params->base.odt); in pctl_cfg()
266 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
267 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
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Dsdram_rk3399.c64 struct rk3399_sdram_params sdram_params;
112 const struct rk3399_sdram_params *sdram_params) in set_memory_map() argument
115 &sdram_params->ch[channel]; in set_memory_map()
151 if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) in set_memory_map()
156 const struct rk3399_sdram_params *sdram_params) in set_ds_odt() argument
166 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
176 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
198 if (sdram_params->base.odt == 1) in set_ds_odt()
295 const struct rk3399_sdram_params *sdram_params) in phy_io_config() argument
305 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
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Dsdram_rk3188.c227 struct rk3188_sdram_params *sdram_params, in pctl_cfg() argument
230 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
231 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
232 switch (sdram_params->base.dramtype) { in pctl_cfg()
234 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
235 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
238 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
241 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
256 struct rk3188_sdram_params *sdram_params) in phy_cfg() argument
260 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
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Dsdram_rk322x.c163 struct rk322x_sdram_params *sdram_params) in memory_init() argument
166 u32 dramtype = sdram_params->base.dramtype; in memory_init()
174 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
179 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
184 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
189 ((sdram_params->phy_timing.mr[0] | in memory_init()
212 (sdram_params->phy_timing.mr[1] & in memory_init()
216 (sdram_params->phy_timing.mr[2] & in memory_init()
220 (sdram_params->phy_timing.mr[3] & in memory_init()
225 (sdram_params->phy_timing.mr11 & in memory_init()
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/external/u-boot/arch/arm/mach-tegra/tegra20/
Dwarmboot.c124 struct sdram_params sdram; in warmboot_save_sdram_params()
142 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), in warmboot_save_sdram_params()
/external/u-boot/arch/arm/include/asm/arch-tegra20/
Dsdram_param.h27 struct sdram_params { struct