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Searched refs:setbits_8 (Results 1 – 25 of 40) sorted by relevance

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/external/u-boot/arch/m68k/cpu/mcf532x/
Dcpu_init.c40 setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); in cpu_init_f()
48 setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); in cpu_init_f()
70 setbits_8(&gpio->par_cs, GPIO_PAR_CS4); in cpu_init_f()
78 setbits_8(&gpio->par_cs, GPIO_PAR_CS5); in cpu_init_f()
125 setbits_8(&gpio->par_uart, in uart_port_conf()
133 setbits_8(&gpio->par_simp1h, in uart_port_conf()
140 setbits_8(&gpio->par_ssih, in uart_port_conf()
147 setbits_8(&gpio->par_uart, in uart_port_conf()
154 setbits_8(&gpio->par_dspih, in uart_port_conf()
161 setbits_8(&gpio->par_feci2c, in uart_port_conf()
[all …]
Dcpu.c26 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
/external/u-boot/arch/m68k/cpu/mcf5445x/
Dcpu_init.c251 setbits_8(&gpio->par_uart0, in uart_port_conf()
259 setbits_8(&gpio->par_uart1, in uart_port_conf()
267 setbits_8(&gpio->par_uart2, in uart_port_conf()
275 setbits_8(&gpio->par_dspi0, in uart_port_conf()
283 setbits_8(&gpio->par_uart0, in uart_port_conf()
291 setbits_8(&gpio->par_uart1, in uart_port_conf()
299 setbits_8(&gpio->par_uart2, in uart_port_conf()
307 setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD); in uart_port_conf()
308 setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD); in uart_port_conf()
315 setbits_8(&gpio->par_cani2c, in uart_port_conf()
[all …]
Dcpu.c27 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
/external/u-boot/board/freescale/mpc8569mds/
Dbcsr.c13 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); in enable_8569mds_flash_write()
24 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), in enable_8569mds_qe_uec()
26 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), in enable_8569mds_qe_uec()
28 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), in enable_8569mds_qe_uec()
30 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), in enable_8569mds_qe_uec()
42 setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); in enable_8569mds_qe_uec()
Dmpc8569mds.c394 setbits_8(&bcsr[15], BCSR15_QEUART_EN); in fdt_board_fixup_qe_uart()
435 setbits_8(&bcsr[6], bcsr6); in board_mmc_init()
490 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD); in fdt_board_fixup_qe_usb()
498 setbits_8(&bcsr[17], BCSR17_USBVCC); in fdt_board_fixup_qe_usb()
499 setbits_8(&bcsr[17], BCSR17_USBMODE); in fdt_board_fixup_qe_usb()
/external/u-boot/arch/m68k/cpu/mcf523x/
Dcpu_init.c60 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); in cpu_init_f()
67 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); in cpu_init_f()
74 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); in cpu_init_f()
81 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); in cpu_init_f()
88 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); in cpu_init_f()
95 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); in cpu_init_f()
102 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); in cpu_init_f()
151 setbits_8(&gpio->par_feci2c, in uart_port_conf()
164 setbits_8(&gpio->par_feci2c, in fecpin_setclear()
/external/u-boot/board/freescale/common/
Dpixis.c233 setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK); in set_altbank()
246 setbits_8(pixis_base + PIXIS_VCTL, 0x1); in set_px_go()
261 setbits_8(pixis_base + PIXIS_VCTL, 0x9); in set_px_go_with_watchdog()
332 setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); in pixis_set_sgmii()
338 setbits_8(pixis_base + PIXIS_VSPEED2, mask); in pixis_set_sgmii()
/external/u-boot/arch/m68k/cpu/mcf52x2/
Dcpu_init.c140 setbits_8(&gpio->par_timer, in uart_port_conf()
146 setbits_8(&gpio->par_feci2c, in uart_port_conf()
152 setbits_8(&gpio->par_feci2c, in uart_port_conf()
165 setbits_8(&gpio->par_fec, in fecpin_setclear()
167 setbits_8(&gpio->par_feci2c, in fecpin_setclear()
520 setbits_8(&gpio->par_fec0hl, 0xc0); in fecpin_setclear()
523 setbits_8(&gpio->par_fec1hl, 0xc0); in fecpin_setclear()
/external/u-boot/board/freescale/p1022ds/
Dp1022ds.c128 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2); in misc_init_r()
141 setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM); in misc_init_r()
145 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI); in misc_init_r()
164 setbits_8(&pixis->brdcfg1, temp); in misc_init_r()
Ddiu.c179 setbits_8(&pixis->csr, PX_CTL_ALTACC); in platform_diu_init()
265 setbits_8(&pixis->csr, PX_CTL_ALTACC); in set_mux_to_diu()
/external/u-boot/drivers/spi/
Dsh_qspi.c110 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); in sh_qspi_init()
119 setbits_8(&ss->regs->spcr, SPCR_SPE); in sh_qspi_init()
138 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST); in spi_cs_activate()
147 setbits_8(&ss->regs->spcr, SPCR_SPE); in spi_cs_activate()
Dmpc8xx_spi.c315 setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ in spi_xfer()
/external/u-boot/board/freescale/m5329evb/
Dnand.c59 setbits_8(&gpio->pddr_timer, 0x08); in board_nand_init()
60 setbits_8(&gpio->ppd_timer, 0x08); in board_nand_init()
/external/u-boot/board/freescale/m5373evb/
Dnand.c63 setbits_8(&gpio->pddr_timer, 0x08); in board_nand_init()
64 setbits_8(&gpio->ppd_timer, 0x08); in board_nand_init()
/external/u-boot/board/keymile/km83xx/
Dkm83xx.c179 setbits_8(&base->pgy_eth, 0x01); in board_early_init_r()
181 setbits_8(&base->oprth, WRL_BOOT); in board_early_init_r()
183 setbits_8(&base->oprtl, OPRTL_XBUFENA); in board_early_init_r()
/external/u-boot/arch/m68k/cpu/mcf5227x/
Dcpu_init.c165 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); in cfspi_claim_bus()
169 setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); in cfspi_claim_bus()
Dcpu.c24 setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
/external/u-boot/board/freescale/m54455evb/
Dm54455evb.c99 setbits_8(&gpio->par_fec, tmp); in ide_preinit()
149 setbits_8(&ata->cr, 0x01); in ide_set_reset()
/external/u-boot/board/freescale/p1010rdb/
Dp1010rdb.c190 setbits_8(&tmp, 0x04); in config_board_mux()
209 setbits_8(&tmp, 0x82); in config_board_mux()
233 setbits_8(&tmp, 0x08); in config_board_mux()
/external/u-boot/board/freescale/m5253evbe/
Dm5253evbe.c125 setbits_8(&ata->cr, 0x01); in ide_set_reset()
/external/u-boot/arch/sandbox/include/asm/
Dio.h109 #define setbits_8(addr, set) setbits(8, addr, set) macro
165 #define setbits_8(addr, set) setbits(8, addr, set) macro
/external/u-boot/board/freescale/m5253demo/
Dm5253demo.c132 setbits_8(&ata->cr, 0x01); in ide_set_reset()
/external/u-boot/board/gdsys/common/
Ddp501.c29 setbits_8(&val, mask); in dp501_setbits()
/external/u-boot/arch/x86/cpu/ivybridge/
Dnorthbridge.c133 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); in northbridge_init()

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