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Searched refs:setbits_be32 (Results 1 – 25 of 127) sorted by relevance

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/external/u-boot/board/gdsys/p1022/
Dcontrolcenterd.c80 setbits_be32(&gur->pmuxcr, 0x00001000); in board_early_init_f()
83 setbits_be32(&gur->pmuxcr, 0x00000010); in board_early_init_f()
86 setbits_be32(&gur->pmuxcr, 0x00000020); in board_early_init_f()
89 setbits_be32(&gur->pmuxcr, 0x000000c0); in board_early_init_f()
92 setbits_be32(&gur->pmuxcr2, 0x03000000); in board_early_init_f()
98 setbits_be32(&gur->pmuxcr, 0x000000F0); in board_early_init_f()
110 setbits_be32(&pgpio->gpdir, 0x00200000); in board_early_init_f()
113 setbits_be32(&pgpio->gpdat, 0x00200000); in board_early_init_f()
121 setbits_be32(&pgpio->gpdir, 0x00100000); in board_early_init_f()
127 setbits_be32(&pgpio->gpdir, 0x00000400); in board_early_init_f()
[all …]
/external/u-boot/board/freescale/p1_p2_rdb_pc/
Dp1_p2_rdb_pc.c154 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); in board_gpio_init()
158 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); in board_gpio_init()
163 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); in board_gpio_init()
166 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); in board_gpio_init()
179 setbits_be32(&pgpio->gpdir, 0x02130000); in board_gpio_init()
182 setbits_be32(&pgpio->gpdir, 0x00200000); in board_gpio_init()
183 setbits_be32(&pgpio->gpodr, 0x00200000); in board_gpio_init()
186 setbits_be32(&pgpio->gpdat, 0x00200000); in board_gpio_init()
193 setbits_be32(&pgpio->gpdir, 0x00080000); in board_gpio_init()
194 setbits_be32(&pgpio->gpdat, 0x00080000); in board_gpio_init()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dcpu_init.c71 setbits_be32(&usb_phy->pllprg[1], in usb_single_source_clk_configure()
112 setbits_be32(&usb_phy->config1, in fsl_erratum_a006261_workaround()
114 setbits_be32(&usb_phy->config2, in fsl_erratum_a006261_workaround()
304 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); in enable_cpc()
307 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); in enable_cpc()
310 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); in enable_cpc()
314 setbits_be32(&cpc->cpchdbcr0, in enable_cpc()
409 setbits_be32(plldadcr1, 0x02000001); in fsl_erratum_a007212_workaround()
411 setbits_be32(plldadcr2, 0x02000001); in fsl_erratum_a007212_workaround()
413 setbits_be32(plldadcr3, 0x02000001); in fsl_erratum_a007212_workaround()
[all …]
Dfsl_corenet_serdes.c238 setbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST); in __serdes_reset_rx()
371 setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1, in p4080_erratum_serdes8()
439 setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1, in p4080_erratum_serdes_a005()
603 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); in fsl_serdes_init()
644 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
647 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
679 setbits_be32(&srds_regs->bank[bank].pllcr0, in fsl_serdes_init()
863 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, in fsl_serdes_init()
/external/u-boot/arch/arm/cpu/armv7/ls102xa/
Dls102xa_psci.c119 setbits_be32(&scfg->hrstcr, 0x80000000); in ls1_start_fsm()
122 setbits_be32(&ddr->sdram_cfg_2, 0x80000000); in ls1_start_fsm()
135 setbits_be32(dcsr_epu_base + EPGCR, 0x80000000); in ls1_start_fsm()
138 setbits_be32(dcsr_epu_base + EPECR15, 0x90000004); in ls1_start_fsm()
168 setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0); in ls1_deep_sleep()
192 setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); in ls1_deep_sleep()
193 setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); in ls1_deep_sleep()
222 setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ); in ls1_sleep()
/external/u-boot/drivers/net/
Dmpc8xx_fec.c305 setbits_be32(&immr->im_cpm.cp_cptr, mask); in fec_10Mbps()
330 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */ in fec_full_duplex()
339 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT); in fec_half_duplex()
380 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001); in fec_pin_init()
386 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003); in fec_pin_init()
387 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003); in fec_pin_init()
402 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001); in fec_pin_init()
405 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100); in fec_pin_init()
434 setbits_be32(&immr->im_ioport.utmode, 0x80); in fec_pin_init()
445 setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc); in fec_pin_init()
[all …]
Dtsec.c119 setbits_be32(&regs->hash.gaddr0 + whichreg, value); in tsec_mcast_addr()
373 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS); in tsec_halt()
413 setbits_be32(&regs->rctrl, 0x8); in redundant_init()
415 setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK); in redundant_init()
417 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); in redundant_init()
420 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS); in redundant_init()
458 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN); in redundant_init()
516 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); in startup_tsec()
519 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS); in startup_tsec()
734 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); in tsec_initialize()
[all …]
/external/u-boot/arch/mips/mach-ath79/
Dreset.c41 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP); in _machine_restart()
95 setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask); in eth_init_ar933x()
128 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); in eth_init_ar934x()
147 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); in eth_init_qca953x()
174 setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, in usb_reset_ar933x()
190 setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, in usb_reset_ar934x()
216 setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, in usb_reset_qca953x()
/external/u-boot/board/varisys/cyrus/
Dcyrus.c46 setbits_be32(&gur->ddrclkdr, 0x001B001B); in board_early_init_f()
49 setbits_be32(&pgpio->gpdat, GPIO_INITIAL); in board_early_init_f()
50 setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN); in board_early_init_f()
53 setbits_be32(&pgpio->gpdir, GPIO_DIR); in board_early_init_f()
/external/u-boot/board/freescale/m5275evb/
Dm5275evb.c47 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); in dram_init()
53 setbits_be32(&sdp->sdmr, in dram_init()
66 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); in dram_init()
71 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); in dram_init()
/external/u-boot/drivers/ddr/fsl/
Dmpc85xx_ddr_gen3.c349 setbits_be32(&ddr->debug[0], 1); in fsl_ddr_set_memctl_regs()
360 setbits_be32(&ecm->eebacr, 0x10000000); in fsl_ddr_set_memctl_regs()
364 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
369 setbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
386 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()
455 setbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
459 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
472 setbits_be32(&ddr->debug[1], 0x800); in fsl_ddr_set_memctl_regs()
484 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
490 setbits_be32(&ddr->debug[1], 0x400); in fsl_ddr_set_memctl_regs()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc8xxx/
Dsrio.c119 setbits_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
126 setbits_be32((void *)&srio_regs->impl.port[port].pcr, in srio_erratum_a004034()
165 setbits_be32(&srds_regs->lane[idx].gcr0, in srio_erratum_a004034()
275 setbits_be32(devdisr, _DEVDISR_SRIO1); in srio_init()
277 setbits_be32(devdisr, _DEVDISR_SRIO2); in srio_init()
282 setbits_be32(devdisr, _DEVDISR_SRIO1); in srio_init()
283 setbits_be32(devdisr, _DEVDISR_SRIO2); in srio_init()
284 setbits_be32(devdisr, _DEVDISR_RMU); in srio_init()
/external/u-boot/board/freescale/b4860qds/
Db4860qds.c610 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
612 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
659 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
682 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
686 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
717 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
733 setbits_be32(&srds_regs->bank[pll_num].pllcr1, in check_pll_locks()
795 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); in config_serdes1_refclks()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dinterrupts.c129 setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec); in cpm_interrupt()
158 setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec); in irq_install_handler()
166 setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec)); in irq_install_handler()
210 setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN); in cpm_interrupt_init()
246 setbits_be32(&immr->im_clkrst.car_plprcr, 0); in timer_interrupt_cpu()
/external/u-boot/board/ve8313/
Dve8313.c79 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
126 setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); in board_early_init_f()
129 setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG); in board_early_init_f()
145 setbits_be32(&gpio->dat, VE8313_WDT_TRIG); in hw_watchdog_reset()
180 setbits_be32(&clk->occr, 0xe0000000); in pci_init_board()
/external/u-boot/board/freescale/bsc9131rdb/
Dbsc9131rdb.c30 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); in board_early_init_f()
33 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | in board_early_init_f()
35 setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); in board_early_init_f()
/external/u-boot/board/freescale/m5235evb/
Dm5235evb.c73 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); in dram_init()
84 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); in dram_init()
92 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); in dram_init()
/external/u-boot/board/freescale/ls1012afrdm/
Deth.c33 setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); in ls1012afrdm_reset_phy()
36 setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); in ls1012afrdm_reset_phy()
40 setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); in ls1012afrdm_reset_phy()
/external/u-boot/board/esd/vme8349/
Dpci.c85 setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N | in pci_init_board()
91 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N); in pci_init_board()
93 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N); in pci_init_board()
/external/u-boot/drivers/phy/
Dbcm6318-usbh-phy.c48 setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN); in bcm6318_usbh_init()
56 setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC); in bcm6318_usbh_init()
62 setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR); in bcm6318_usbh_init()
/external/u-boot/board/freescale/mpc8308rdb/
Dmpc8308rdb.c47 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); in spi_cs_deactivate()
146 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); in misc_init_r()
147 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); in misc_init_r()
/external/u-boot/arch/m68k/cpu/mcf5227x/
Dinterrupts.c21 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init()
22 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init()
/external/u-boot/arch/m68k/cpu/mcf547x_8x/
Dinterrupts.c18 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init()
19 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init()
/external/u-boot/arch/m68k/cpu/mcf5445x/
Dinterrupts.c21 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init()
22 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init()
/external/u-boot/arch/m68k/cpu/mcf532x/
Dinterrupts.c18 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init()
19 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init()

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