| /external/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-SHADD16-arm.txt | 4 # CHECK: shadd16 r5, r7, r0
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| D | basic-arm-instructions.txt | 1535 # CHECK: shadd16 r4, r8, r2
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-SHADD16-arm.txt | 4 # CHECK: shadd16 r5, r7, r0
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| D | basic-arm-instructions.txt | 1535 # CHECK: shadd16 r4, r8, r2
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 214 define i32 @shadd16(i32 %a, i32 %b) nounwind {
215 ; CHECK-LABEL: shadd16
216 ; CHECK: shadd16 r0, r0, r1
217 %tmp = call i32 @llvm.arm.shadd16(i32 %a, i32 %b)
452 declare i32 @llvm.arm.shadd16(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 61 M(shadd16) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 60 M(shadd16) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 631 0x12,0x4f,0x38,0xe6 = shadd16 r4, r8, r2
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1545 shadd16 r4, r8, r2
1550 @ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3029 void shadd16(Condition cond, Register rd, Register rn, Register rm);
3030 void shadd16(Register rd, Register rn, Register rm) { in shadd16() function
3031 shadd16(al, rd, rn, rm); in shadd16()
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| D | disasm-aarch32.h | 1073 void shadd16(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2482 void Disassembler::shadd16(Condition cond, in shadd16() function in vixl::aarch32::Disassembler
21568 shadd16(CurrentCond(), in DecodeT32()
62591 shadd16(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 9679 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) { in shadd16() function in vixl::aarch32::Assembler
9699 Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm); in shadd16()
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| D | macro-assembler-aarch32.h | 3452 shadd16(cond, rd, rn, rm); in Shadd16()
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2327 shadd16 r4, r8, r2
2332 @ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2329 shadd16 r4, r8, r2
2334 @ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1374 # CHECK: shadd16 r4, r8, r2
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1971 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
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| D | ARMInstrInfo.td | 3204 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2244 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
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| D | ARMInstrInfo.td | 3750 def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2176 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
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| D | ARMInstrInfo.td | 3605 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7753 "sha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003"
8660 …{ 935 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb…
8661 …{ 935 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { …
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1165 arm_shadd16, // llvm.arm.shadd16
|