| /external/unicode/ |
| D | CVTUTF7.C | 91 int shifted = 0, needshift = 0, done = 0; in ConvertUCS2toUTF7() local
112 if (needshift && !shifted) in ConvertUCS2toUTF7()
122 shifted = 1; in ConvertUCS2toUTF7()
125 if (shifted) in ConvertUCS2toUTF7()
159 shifted = 0; in ConvertUCS2toUTF7()
184 int shifted = 0, first = 0, wroteone = 0, base64EOF, base64value, done; in ConvertUTF7toUCS2() local
198 if (shifted) in ConvertUTF7toUCS2()
206 shifted = 0; in ConvertUTF7toUCS2()
272 if (!shifted && !done) in ConvertUTF7toUCS2()
276 shifted = 1; in ConvertUTF7toUCS2()
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| /external/libaom/libaom/av1/common/x86/ |
| D | av1_convolve_scale_sse4.c | 80 __m128i shifted = in hfilter8() local
83 shifted = _mm_packus_epi32(shifted, shifted); in hfilter8()
85 _mm_storel_epi64((__m128i *)(dst + y + x * h), shifted); in hfilter8()
167 __m128i shifted = in vfilter8() local
173 __m128i shifted_16 = _mm_packus_epi32(shifted, shifted); in vfilter8()
311 __m128i shifted = in highbd_hfilter8() local
314 shifted = _mm_packus_epi32(shifted, shifted); in highbd_hfilter8()
316 _mm_storel_epi64((__m128i *)(dst + y + x * h), shifted); in highbd_hfilter8()
399 __m128i shifted = in highbd_vfilter8() local
412 shifted = _mm_add_epi32(_mm_mullo_epi32(p_32, wt0), in highbd_vfilter8()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | insert-05.ll | 90 %shifted = lshr i64 %a, 1
91 %and = and i64 %shifted, 18446744069414584320
102 %shifted = lshr i64 %a, 1
103 %and = and i64 %shifted, 18446744069414584320
114 %shifted = lshr i64 %a, 1
115 %and = and i64 %shifted, 9223372032559808512
126 %shifted = lshr i64 %a, 1
127 %and = and i64 %shifted, 9223372032559808512
172 %shifted = shl i64 %a, 1
173 %and = and i64 %shifted, 4294967295
[all …]
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| D | rnsbg-01.ll | 92 ; Test a case with a left shift and OR, where the OR covers all shifted bits.
116 ; shifted bits. We can't use RNSBG for the shift, but we can for the OR
141 ; Test a case with a right shift and OR, where the OR covers all the shifted
165 ; shifted bits. The shift needs to be done separately, but the OR and AND
245 ; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
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| D | risbg-04.ll | 6 ; Test an extraction of bit 0 from a right-shifted value.
26 ; Test an extraction of other bits from a right-shifted value.
46 ; Test an extraction of most bits from a right-shifted value.
90 ; Test an extraction of bits from a left-shifted value. The range should
257 ; Check that we use RISBG for shifted values even if the AND is a
433 ; Try a similar thing in which no shifted sign bits are kept.
472 ; when testing whether the shifted-in bits of the shift right were significant.
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | insert-05.ll | 90 %shifted = lshr i64 %a, 1
91 %and = and i64 %shifted, 18446744069414584320
102 %shifted = lshr i64 %a, 1
103 %and = and i64 %shifted, 18446744069414584320
114 %shifted = lshr i64 %a, 1
115 %and = and i64 %shifted, 9223372032559808512
126 %shifted = lshr i64 %a, 1
127 %and = and i64 %shifted, 9223372032559808512
172 %shifted = shl i64 %a, 1
173 %and = and i64 %shifted, 4294967295
[all …]
|
| D | rnsbg-01.ll | 92 ; Test a case with a left shift and OR, where the OR covers all shifted bits.
116 ; shifted bits. We can't use RNSBG for the shift, but we can for the OR
141 ; Test a case with a right shift and OR, where the OR covers all the shifted
165 ; shifted bits. The shift needs to be done separately, but the OR and AND
245 ; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
|
| D | risbg-01.ll | 6 ; Test an extraction of bit 0 from a right-shifted value.
26 ; Test an extraction of other bits from a right-shifted value.
46 ; Test an extraction of most bits from a right-shifted value.
90 ; Test an extraction of bits from a left-shifted value. The range should
257 ; Check that we use RISBG for shifted values even if the AND is a
433 ; Try a similar thing in which no shifted sign bits are kept.
472 ; when testing whether the shifted-in bits of the shift right were significant.
|
| /external/pdfium/core/fxcodec/jbig2/ |
| D | JBig2_HuffmanTable.cpp | 124 pdfium::base::CheckedNumeric<int> shifted; in InitCodes() local
125 shifted = FIRSTCODE[i - 1] + LENCOUNT[i - 1]; in InitCodes()
126 shifted <<= 1; in InitCodes()
127 if (!shifted.IsValid()) in InitCodes()
130 FIRSTCODE[i] = shifted.ValueOrDie(); in InitCodes()
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| /external/libvpx/libvpx/vp8/common/x86/ |
| D | bilinear_filter_sse2.c | 176 const __m128i shifted = _mm_srai_epi16(compensated, VP8_FILTER_SHIFT); in horizontal_8xN() local
177 _mm_store_si128((__m128i *)dst, shifted); in horizontal_8xN()
212 const __m128i shifted = _mm_srai_epi16(compensated, VP8_FILTER_SHIFT); in vertical_8xN() local
213 const __m128i packed = _mm_packus_epi16(shifted, shifted); in vertical_8xN()
276 const __m128i shifted = _mm_srai_epi16(compensated, VP8_FILTER_SHIFT); in horizontal_4x4() local
277 _mm_storel_epi64((__m128i *)dst, shifted); in horizontal_4x4()
314 const __m128i shifted = _mm_srai_epi16(compensated, VP8_FILTER_SHIFT); in vertical_4x4() local
315 __m128i packed = _mm_packus_epi16(shifted, shifted); in vertical_4x4()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | bitfield.ll | 200 %shifted = lshr i32 %fields, 23
201 %masked = and i32 %shifted, 7
209 %shifted = lshr i64 %fields, 25
210 %masked = and i64 %shifted, 1023
219 %shifted = shl i32 %fields, 23
220 %extended = ashr i32 %shifted, 29
229 %shifted = shl i64 %fields, 1
230 %extended = ashr i64 %shifted, 1
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| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield.ll | 200 %shifted = lshr i32 %fields, 23
201 %masked = and i32 %shifted, 7
209 %shifted = lshr i64 %fields, 25
210 %masked = and i64 %shifted, 1023
219 %shifted = shl i32 %fields, 23
220 %extended = ashr i32 %shifted, 29
229 %shifted = shl i64 %fields, 1
230 %extended = ashr i64 %shifted, 1
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_nir_lower_multiview.c | 109 nir_ssa_def *shifted; in build_view_index() local
111 shifted = nir_ushr(b, nir_imm_int(b, remap), shift); in build_view_index()
118 shifted = nir_bcsel(b, nir_ilt(b, shift, nir_imm_int(b, 32)), in build_view_index()
121 state->view_index = nir_iand(b, shifted, nir_imm_int(b, 0xf)); in build_view_index()
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| /external/tensorflow/tensorflow/core/api_def/base_api/ |
| D | api_def_Roll.pbtxt | 7 elements are shifted positively (towards larger indices) along the dimension
24 Has the same shape and size as the input. The elements are shifted
31 The elements are shifted positively (towards larger indices) by the offset of
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| /external/boringssl/src/crypto/hrss/ |
| D | hrss_test.cc | 56 struct poly2 p, orig, shifted; in TEST() local
68 poly2_from_bits(&shifted, bits); in TEST()
70 Bytes(reinterpret_cast<const uint8_t *>(&shifted), sizeof(shifted)), in TEST()
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| /external/boringssl/src/ssl/test/runner/hrss/ |
| D | hrss.go | 334 var shifted poly3
338 shifted.rotWords(1<<shift, p)
339 p.cmov(&shifted, lsbToAll(bits>>shift))
342 shifted.rotBits(1<<shift, p)
343 p.cmov(&shifted, lsbToAll(bits>>shift))
484 var shifted [wordsPerPoly]uint
489 rotWords(&shifted, out, 1<<shift)
490 cmovWords(out, &shifted, lsbToAll(bits>>shift))
493 rotBits(&shifted, out, 1<<shift)
494 cmovWords(out, &shifted, lsbToAll(bits>>shift))
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_format_srgb.c | 357 LLVMValueRef shifted, shift_val; in lp_build_float_to_srgb_packed() local
360 shifted = LLVMBuildShl(builder, tmpsrgb[chan], shift_val, ""); in lp_build_float_to_srgb_packed()
361 dst = LLVMBuildOr(builder, dst, shifted, ""); in lp_build_float_to_srgb_packed()
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| D | lp_bld_swizzle.c | 536 LLVMValueRef shifted; in lp_build_swizzle_aos() local
543 shifted = LLVMBuildShl(builder, masked, in lp_build_swizzle_aos()
546 shifted = LLVMBuildLShr(builder, masked, in lp_build_swizzle_aos()
549 shifted = masked; in lp_build_swizzle_aos()
552 res = LLVMBuildOr(builder, res, shifted, ""); in lp_build_swizzle_aos()
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| D | lp_bld_format_aos.c | 226 LLVMValueRef shifted, casted, scaled, masked; in lp_build_unpack_arith_rgba_aos() local
328 shifted = LLVMBuildLShr(builder, packed, LLVMConstVector(shifts, 4), ""); in lp_build_unpack_arith_rgba_aos()
329 masked = LLVMBuildAnd(builder, shifted, LLVMConstVector(masks, 4), ""); in lp_build_unpack_arith_rgba_aos()
372 LLVMValueRef shifted, casted, scaled, unswizzled; in lp_build_pack_rgba_aos() local
433 shifted = LLVMBuildShl(builder, casted, LLVMConstVector(shifts, 4), ""); in lp_build_pack_rgba_aos()
438 LLVMValueRef component = LLVMBuildExtractElement(builder, shifted, in lp_build_pack_rgba_aos()
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| /external/llvm/test/CodeGen/X86/ |
| D | trunc-to-bool.ll | 15 %shifted = ashr i32 %val, %mask
16 %anded = and i32 %shifted, 1
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| D | urem-power-of-two.ll | 17 ; A left-shifted power-of-2 divisor. Use a weird type for wider coverage.
34 ; FIXME: A logically right-shifted sign bit is a power-of-2 or UB.
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | trunc-to-bool.ll | 15 %shifted = ashr i32 %val, %mask
16 %anded = and i32 %shifted, 1
|
| /external/u-boot/doc/device-tree-bindings/exynos/ |
| D | dwmmc.txt | 33 . SelClk_sample: Select sample clock among 8 shifted clocks.
34 . SelClk_drv: Select drv clock among 8 shifted clocks.
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_shiftrountine_with_rnd_eld.s | 43 … r10, r4, ASR #0x16 @Right shift by 22 to check the overflow ( is not AAC_ELD right shifted by 21)
48 … MOVEQ r4, r4, LSL #9 @shift by 9(hardcoded value) if not AAC_ELD left shifted by 10
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| /external/icu/icu4c/source/data/coll/ |
| D | th.txt | 9 "[alternate shifted]"
|