| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 228 define i32 @shsax(i32 %a, i32 %b) nounwind {
229 ; CHECK-LABEL: shsax
230 ; CHECK: shsax r0, r0, r1
231 %tmp = call i32 @llvm.arm.shsax(i32 %a, i32 %b)
454 declare i32 @llvm.arm.shsax(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 64 M(shsax) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 63 M(shsax) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 702 0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2
705 0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1794 shsax r4, r8, r2
1801 @ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4]
1804 @ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2277 shsax r4, r8, r2
2284 @ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4]
2287 @ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2229 shsax r4, r8, r2
2236 @ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4]
2239 @ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3040 void shsax(Condition cond, Register rd, Register rn, Register rm);
3041 void shsax(Register rd, Register rn, Register rm) { shsax(al, rd, rn, rm); } in shsax() function
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| D | disasm-aarch32.h | 1079 void shsax(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2521 void Disassembler::shsax(Condition cond, in shsax() function in vixl::aarch32::Disassembler
21487 shsax(CurrentCond(), in DecodeT32()
62694 shsax(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
|
| D | assembler-aarch32.cc | 9748 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) { in shsax() function in vixl::aarch32::Assembler
9768 Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm); in shsax()
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| D | macro-assembler-aarch32.h | 3490 shsax(cond, rd, rn, rm); in Shsax()
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1580 # CHECK: shsax r4, r8, r2
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1719 # CHECK: shsax r4, r8, r2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1719 # CHECK: shsax r4, r8, r2
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3206 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
4979 def : MnemonicAlias<"shsubaddx", "shsax">;
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| D | ARMInstrThumb2.td | 1973 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3752 def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>;
5989 def : MnemonicAlias<"shsubaddx", "shsax">;
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| D | ARMInstrThumb2.td | 2246 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3607 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
5689 def : MnemonicAlias<"shsubaddx", "shsax">;
|
| D | ARMInstrThumb2.td | 2178 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1357 Mnemonic = "shsax"; // "shsubaddx"
7753 "sha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003"
8666 …{ 956 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Fe…
8667 …{ 956 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_…
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1168 arm_shsax, // llvm.arm.shsax
|
| D | IntrinsicImpl.inc | 1194 "llvm.arm.shsax",
10072 1, // llvm.arm.shsax
|