| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 107 define i32 @shsub8(i32 %a, i32 %b) nounwind {
108 ; CHECK-LABEL: shsub8
109 ; CHECK: shsub8 r0, r0, r1
110 %tmp = call i32 @llvm.arm.shsub8(i32 %a, i32 %b)
436 declare i32 @llvm.arm.shsub8(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 66 M(shsub8) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 65 M(shsub8) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 639 0xf2,0x4f,0x38,0xe6 = shsub8 r4, r8, r2
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| D | basic-thumb2-instructions.s.cs | 709 0xc8,0xfa,0x22,0xf4 = shsub8 r4, r8, r2
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1571 shsub8 r4, r8, r2
1576 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
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| D | basic-thumb2-instructions.s | 1813 shsub8 r4, r8, r2
1819 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3048 void shsub8(Condition cond, Register rd, Register rn, Register rm);
3049 void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); } in shsub8() function
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| D | disasm-aarch32.h | 1083 void shsub8(Condition cond, Register rd, Register rn, Register rm);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2296 shsub8 r4, r8, r2
2302 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4]
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| D | basic-arm-instructions.s | 2355 shsub8 r4, r8, r2
2360 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2353 shsub8 r4, r8, r2
2358 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6]
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| D | basic-thumb2-instructions.s | 2248 shsub8 r4, r8, r2
2254 @ CHECK: shsub8 r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1400 # CHECK: shsub8 r4, r8, r2
|
| D | thumb2.txt | 1593 # CHECK: shsub8 r4, r8, r2
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1732 # CHECK: shsub8 r4, r8, r2
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| D | basic-arm-instructions.txt | 1561 # CHECK: shsub8 r4, r8, r2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1561 # CHECK: shsub8 r4, r8, r2
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| D | thumb2.txt | 1732 # CHECK: shsub8 r4, r8, r2
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1975 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
|
| D | ARMInstrInfo.td | 3208 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2248 def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>;
|
| D | ARMInstrInfo.td | 3754 def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2180 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7753 "sha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003"
8670 …{ 970 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|…
8671 …{ 970 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MC…
|