| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 354 define i64 @smlald(i32 %a, i32 %b, i64 %c) nounwind {
355 ; CHECK-LABEL: smlald
356 ; CHECK: smlald r2, r3, r0, r1
357 %tmp = call i64 @llvm.arm.smlald(i32 %a, i32 %b, i64 %c)
472 declare i64 @llvm.arm.smlald(i32, i32, i64) nounwind
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 665 0x15,0x28,0x43,0xe7 = smlald r2, r3, r5, r8
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| D | basic-thumb2-instructions.s.cs | 739 0xc5,0xfb,0xc8,0x23 = smlald r2, r3, r5, r8
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1662 smlald r2, r3, r5, r8
1667 @ CHECK: smlald r2, r3, r5, r8 @ encoding: [0x15,0x28,0x43,0xe7]
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| D | basic-thumb2-instructions.s | 1904 smlald r2, r3, r5, r8
1910 @ CHECK: smlald r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xc8,0x23]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3093 void smlald(
3095 void smlald(Register rdlo, Register rdhi, Register rn, Register rm) { in smlald() function
3096 smlald(al, rdlo, rdhi, rn, rm); in smlald()
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| D | disasm-aarch32.h | 1106 void smlald(
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| D | disasm-aarch32.cc | 2609 void Disassembler::smlald( in smlald() function in vixl::aarch32::Disassembler
22484 smlald(CurrentCond(), in DecodeT32()
64162 smlald(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 10000 void Assembler::smlald( in smlald() function in vixl::aarch32::Assembler
10024 Delegate(kSmlald, &Assembler::smlald, cond, rdlo, rdhi, rn, rm); in smlald()
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| D | macro-assembler-aarch32.h | 3642 smlald(cond, rdlo, rdhi, rn, rm); in Smlald()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2387 smlald r2, r3, r5, r8
2393 @ CHECK: smlald r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xc8,0x23]
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| D | basic-arm-instructions.s | 2437 smlald r2, r3, r5, r8
2442 @ CHECK: smlald r2, r3, r5, r8 @ encoding: [0x15,0x28,0x43,0xe7]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2435 smlald r2, r3, r5, r8
2440 @ CHECK: smlald r2, r3, r5, r8 @ encoding: [0x15,0x28,0x43,0xe7]
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| D | basic-thumb2-instructions.s | 2339 smlald r2, r3, r5, r8
2345 @ CHECK: smlald r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xc8,0x23]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1491 # CHECK: smlald r2, r3, r5, r8
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| D | thumb2.txt | 1683 # CHECK: smlald r2, r3, r5, r8
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1822 # CHECK: smlald r2, r3, r5, r8
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| D | basic-arm-instructions.txt | 1643 # CHECK: smlald r2, r3, r5, r8
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1643 # CHECK: smlald r2, r3, r5, r8
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| D | thumb2.txt | 1822 # CHECK: smlald r2, r3, r5, r8
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2665 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2869 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2893 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7755 "bt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006smlatt\006sm"
8689 …{ 1030 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__C…
8690 …{ 1030 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__Con…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1175 arm_smlald, // llvm.arm.smlald
|