/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | smul.ll | 31 ; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}} 32 ; CHECK-THUMBV6-NOT: {{smlabt|smlatb}} 66 ; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}} 67 ; CHECK-THUMBV6-NOT: {{smlatb|smlabt}} 218 ; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}} 219 ; CHECK-THUMBV6-NOT: {{smlabt|smlatb}} 230 ; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}} 231 ; CHECK-THUMBV6-NOT: {{smlatb|smlabt}}
|
D | acle-intrinsics-v5.ll | 54 ; CHECK: smlatb r2, r0, r1, r2 60 %acc3 = call i32 @llvm.arm.smlatb(i32 %a, i32 %b, i32 %acc2) 105 declare i32 @llvm.arm.smlatb(i32, i32, i32) nounwind
|
/external/webrtc/webrtc/common_audio/signal_processing/ |
D | filter_ar_fast_q12_armv7.S | 66 smlatb r7, r10, r5, r7 @ sum1 += coefficients[j] * data_out[i - j]; 82 smlatb r7, r10, r5, r7 @ sum1 += coefficients[1] * data_out[i - 1]; 95 smlatb r8, r10, r6, r8 @ sum2 += coefficients[1] * data_out[i];
|
/external/arm-neon-tests/ |
D | ref_dsp.c | 298 sres = smlatb(svar1, svar2, sacc); in exec_dsp() 309 sres = smlatb(svar1, svar2, sacc); in exec_dsp()
|
D | ref-rvct-all.txt | 8016 smlatb(0x12345678, 0x12345678, 0x1020304) = 0x7280364 8020 smlatb(0xf123f456, 0xf123f456, 0x1020304) = 0x1af60c6
|
/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 643 0xa2,0x23,0x04,0xe1 = smlatb r4, r2, r3, r2
|
D | basic-thumb2-instructions.s.cs | 715 0x12,0xfb,0x23,0x24 = smlatb r4, r2, r3, r2
|
/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 1593 smlatb r4, r2, r3, r2 1602 @ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0xa2,0x23,0x04,0xe1]
|
D | basic-thumb2-instructions.s | 1830 smlatb r4, r2, r3, r2 1840 @ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0x12,0xfb,0x23,0x24]
|
/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3123 void smlatb( 3125 void smlatb(Register rd, Register rn, Register rm, Register ra) { in smlatb() function 3126 smlatb(al, rd, rn, rm, ra); in smlatb()
|
D | disasm-aarch32.h | 1121 void smlatb(
|
D | disasm-aarch32.cc | 2644 void Disassembler::smlatb( in smlatb() function in vixl::aarch32::Disassembler 22150 smlatb(CurrentCond(), in DecodeT32() 56237 smlatb(condition, in DecodeA32()
|
D | assembler-aarch32.cc | 10126 void Assembler::smlatb( in smlatb() function in vixl::aarch32::Assembler 10149 Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra); in smlatb()
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | basic-thumb2-instructions.s | 2313 smlatb r4, r2, r3, r2 2323 @ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0x12,0xfb,0x23,0x24]
|
D | basic-arm-instructions.s | 2368 smlatb r4, r2, r3, r2 2377 @ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0xa2,0x23,0x04,0xe1]
|
/external/llvm/test/MC/ARM/ |
D | basic-arm-instructions.s | 2366 smlatb r4, r2, r3, r2 2375 @ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0xa2,0x23,0x04,0xe1]
|
D | basic-thumb2-instructions.s | 2265 smlatb r4, r2, r3, r2 2275 @ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0x12,0xfb,0x23,0x24]
|
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1422 # CHECK: smlatb r4, r2, r3, r2
|
D | thumb2.txt | 1610 # CHECK: smlatb r4, r2, r3, r2
|
/external/llvm/test/MC/Disassembler/ARM/ |
D | thumb2.txt | 1749 # CHECK: smlatb r4, r2, r3, r2
|
D | basic-arm-instructions.txt | 1574 # CHECK: smlatb r4, r2, r3, r2
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1574 # CHECK: smlatb r4, r2, r3, r2
|
D | thumb2.txt | 1749 # CHECK: smlatb r4, r2, r3, r2
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2776 def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
|
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 7755 "bt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006smlatt\006sm" 8697 …{ 1061 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_… 8698 …{ 1061 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…
|