/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | acle-intrinsics-v5.ll | 57 ; CHECK: smlawt r0, r0, r1, r2 63 %acc6 = call i32 @llvm.arm.smlawt(i32 %a, i32 %b, i32 %acc5) 108 declare i32 @llvm.arm.smlawt(i32, i32, i32) nounwind
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D | smul.ll | 106 ; CHECK: smlawt r0, r0, r1, r2 107 ; CHECK-THUMBV6-NOT: smlawt
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/external/arm-neon-tests/ |
D | ref_dsp.c | 411 sres = smlawt(svar1, svar2, sacc); in exec_dsp() 418 sres = smlawt(svar1, svar2, sacc); in exec_dsp()
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D | ref-rvct-all.txt | 8039 smlawt(0x12345678, 0x12345678, 0x1020304) = 0x24d63ba 8041 smlawt(0xf123f456, 0xf123f456, 0X1020304) = 0x1dedf9d
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/external/llvm/test/CodeGen/ARM/ |
D | smul.ll | 96 ; CHECK: smlawt
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/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 670 0xc3,0x95,0x28,0xe1 = smlawt r8, r3, r5, r9
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D | basic-thumb2-instructions.s.cs | 745 0x33,0xfb,0x15,0x98 = smlawt r8, r3, r5, r9
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 1677 smlawt r8, r3, r5, r9 1682 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
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D | basic-thumb2-instructions.s | 1921 smlawt r8, r3, r5, r9 1927 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3141 void smlawt( 3143 void smlawt(Register rd, Register rn, Register rm, Register ra) { in smlawt() function 3144 smlawt(al, rd, rn, rm, ra); in smlawt()
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D | disasm-aarch32.h | 1130 void smlawt(
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D | disasm-aarch32.cc | 2665 void Disassembler::smlawt( in smlawt() function in vixl::aarch32::Disassembler 22255 smlawt(CurrentCond(), in DecodeT32() 56576 smlawt(condition, in DecodeA32()
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D | assembler-aarch32.cc | 10204 void Assembler::smlawt( in smlawt() function in vixl::aarch32::Assembler 10227 Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra); in smlawt()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | basic-thumb2-instructions.s | 2404 smlawt r8, r3, r5, r9 2410 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
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D | basic-arm-instructions.s | 2452 smlawt r8, r3, r5, r9 2457 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
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/external/llvm/test/MC/ARM/ |
D | basic-arm-instructions.s | 2450 smlawt r8, r3, r5, r9 2455 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
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D | basic-thumb2-instructions.s | 2356 smlawt r8, r3, r5, r9 2362 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1506 # CHECK: smlawt r8, r3, r5, r9
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D | thumb2.txt | 1700 # CHECK: smlawt r8, r3, r5, r9
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/external/llvm/test/MC/Disassembler/ARM/ |
D | thumb2.txt | 1839 # CHECK: smlawt r8, r3, r5, r9
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D | basic-arm-instructions.txt | 1658 # CHECK: smlawt r8, r3, r5, r9
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1658 # CHECK: smlawt r8, r3, r5, r9
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D | thumb2.txt | 1839 # CHECK: smlawt r8, r3, r5, r9
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2784 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 7756 "lawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smml" 8703 …{ 1082 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_… 8704 …{ 1082 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…
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