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Searched refs:smlawt (Results 1 – 25 of 28) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dacle-intrinsics-v5.ll57 ; CHECK: smlawt r0, r0, r1, r2
63 %acc6 = call i32 @llvm.arm.smlawt(i32 %a, i32 %b, i32 %acc5)
108 declare i32 @llvm.arm.smlawt(i32, i32, i32) nounwind
Dsmul.ll106 ; CHECK: smlawt r0, r0, r1, r2
107 ; CHECK-THUMBV6-NOT: smlawt
/external/arm-neon-tests/
Dref_dsp.c411 sres = smlawt(svar1, svar2, sacc); in exec_dsp()
418 sres = smlawt(svar1, svar2, sacc); in exec_dsp()
Dref-rvct-all.txt8039 smlawt(0x12345678, 0x12345678, 0x1020304) = 0x24d63ba
8041 smlawt(0xf123f456, 0xf123f456, 0X1020304) = 0x1dedf9d
/external/llvm/test/CodeGen/ARM/
Dsmul.ll96 ; CHECK: smlawt
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs670 0xc3,0x95,0x28,0xe1 = smlawt r8, r3, r5, r9
Dbasic-thumb2-instructions.s.cs745 0x33,0xfb,0x15,0x98 = smlawt r8, r3, r5, r9
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1677 smlawt r8, r3, r5, r9
1682 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
Dbasic-thumb2-instructions.s1921 smlawt r8, r3, r5, r9
1927 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3141 void smlawt(
3143 void smlawt(Register rd, Register rn, Register rm, Register ra) { in smlawt() function
3144 smlawt(al, rd, rn, rm, ra); in smlawt()
Ddisasm-aarch32.h1130 void smlawt(
Ddisasm-aarch32.cc2665 void Disassembler::smlawt( in smlawt() function in vixl::aarch32::Disassembler
22255 smlawt(CurrentCond(), in DecodeT32()
56576 smlawt(condition, in DecodeA32()
Dassembler-aarch32.cc10204 void Assembler::smlawt( in smlawt() function in vixl::aarch32::Assembler
10227 Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra); in smlawt()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s2404 smlawt r8, r3, r5, r9
2410 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
Dbasic-arm-instructions.s2452 smlawt r8, r3, r5, r9
2457 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2450 smlawt r8, r3, r5, r9
2455 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1]
Dbasic-thumb2-instructions.s2356 smlawt r8, r3, r5, r9
2362 @ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1506 # CHECK: smlawt r8, r3, r5, r9
Dthumb2.txt1700 # CHECK: smlawt r8, r3, r5, r9
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1839 # CHECK: smlawt r8, r3, r5, r9
Dbasic-arm-instructions.txt1658 # CHECK: smlawt r8, r3, r5, r9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1658 # CHECK: smlawt r8, r3, r5, r9
Dthumb2.txt1839 # CHECK: smlawt r8, r3, r5, r9
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2784 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7756 "lawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smml"
8703 …{ 1082 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_…
8704 …{ 1082 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…

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