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Searched refs:smmls (Results 1 – 25 of 29) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dsmml.ll14 ; CHECK-NOT: smmls
27 ;CHECK-V4-NOT: smmls
28 ;CHECK-THUMB-NOT: smmls
29 ;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
30 ;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
Ddsp-mlal.ll95 ; CHECK: smmls r0, {{(r1, r2|r2, r1)}}, r0
97 ; NODSP-NOT: smmls
112 ; CHECK-NOT: smmls
114 ; NODSP-NOT: smmls
/external/llvm/test/CodeGen/ARM/
Dsmml.ll5 ; CHECK-NOT: smmls
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs685 0xd2,0x43,0x51,0xe7 = smmls r1, r2, r3, r4
Dbasic-thumb2-instructions.s.cs764 0x62,0xfb,0x03,0x41 = smmls r1, r2, r3, r4
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1732 smmls r1, r2, r3, r4
1737 @ CHECK: smmls r1, r2, r3, r4 @ encoding: [0xd2,0x43,0x51,0xe7]
Dbasic-thumb2-instructions.s1984 smmls r1, r2, r3, r4
1990 @ CHECK: smmls r1, r2, r3, r4 @ encoding: [0x62,0xfb,0x03,0x41]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3183 void smmls(
3185 void smmls(Register rd, Register rn, Register rm, Register ra) { in smmls() function
3186 smmls(al, rd, rn, rm, ra); in smmls()
Ddisasm-aarch32.h1151 void smmls(
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s2467 smmls r1, r2, r3, r4
2473 @ CHECK: smmls r1, r2, r3, r4 @ encoding: [0x62,0xfb,0x03,0x41]
Dbasic-arm-instructions.s2507 smmls r1, r2, r3, r4
2512 @ CHECK: smmls r1, r2, r3, r4 @ encoding: [0xd2,0x43,0x51,0xe7]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2505 smmls r1, r2, r3, r4
2510 @ CHECK: smmls r1, r2, r3, r4 @ encoding: [0xd2,0x43,0x51,0xe7]
Dbasic-thumb2-instructions.s2419 smmls r1, r2, r3, r4
2425 @ CHECK: smmls r1, r2, r3, r4 @ encoding: [0x62,0xfb,0x03,0x41]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1561 # CHECK: smmls r1, r2, r3, r4
Dthumb2.txt1763 # CHECK: smmls r1, r2, r3, r4
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1902 # CHECK: smmls r1, r2, r3, r4
Dbasic-arm-instructions.txt1713 # CHECK: smmls r1, r2, r3, r4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1713 # CHECK: smmls r1, r2, r3, r4
Dthumb2.txt1902 # CHECK: smmls r1, r2, r3, r4
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td2419 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
DARMInstrInfo.td3593 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2702 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
DARMInstrInfo.td4200 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2651 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7757 "ar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006"
8717 …{ 1130 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Is…
8718 …{ 1130 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsAR…

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