| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 403 define i32 @smuadx(i32 %a, i32 %b) nounwind {
404 ;CHECK-LABEL: smuadx
405 ; CHECK: smuadx r0, r0, r1
406 %tmp = call i32 @llvm.arm.smuadx(i32 %a, i32 %b)
479 declare i32 @llvm.arm.smuadx(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 70 M(smuadx) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 69 M(smuadx) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 694 0x32,0xf1,0x03,0xe7 = smuadx r3, r2, r1
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| D | basic-thumb2-instructions.s.cs | 775 0x22,0xfb,0x11,0xf3 = smuadx r3, r2, r1
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1761 smuadx r3, r2, r1
1766 @ CHECK: smuadx r3, r2, r1 @ encoding: [0x32,0xf1,0x03,0xe7]
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| D | basic-thumb2-instructions.s | 2017 smuadx r3, r2, r1
2023 @ CHECK: smuadx r3, r2, r1 @ encoding: [0x22,0xfb,0x11,0xf3]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3204 void smuadx(Condition cond, Register rd, Register rn, Register rm);
3205 void smuadx(Register rd, Register rn, Register rm) { smuadx(al, rd, rn, rm); } in smuadx() function
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| D | disasm-aarch32.h | 1163 void smuadx(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2767 void Disassembler::smuadx(Condition cond, in smuadx() function in vixl::aarch32::Disassembler
21922 smuadx(CurrentCond(), in DecodeT32()
63801 smuadx(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 10505 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) { in smuadx() function in vixl::aarch32::Assembler
10525 Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm); in smuadx()
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| D | macro-assembler-aarch32.h | 3948 smuadx(cond, rd, rn, rm); in Smuadx()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2500 smuadx r3, r2, r1
2506 @ CHECK: smuadx r3, r2, r1 @ encoding: [0x22,0xfb,0x11,0xf3]
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| D | basic-arm-instructions.s | 2536 smuadx r3, r2, r1
2541 @ CHECK: smuadx r3, r2, r1 @ encoding: [0x32,0xf1,0x03,0xe7]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2534 smuadx r3, r2, r1
2539 @ CHECK: smuadx r3, r2, r1 @ encoding: [0x32,0xf1,0x03,0xe7]
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| D | basic-thumb2-instructions.s | 2452 smuadx r3, r2, r1
2458 @ CHECK: smuadx r3, r2, r1 @ encoding: [0x22,0xfb,0x11,0xf3]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1590 # CHECK: smuadx r3, r2, r1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1742 # CHECK: smuadx r3, r2, r1
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1742 # CHECK: smuadx r3, r2, r1
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2630 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2842 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2858 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7757 "ar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006"
8727 …{ 1162 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2…
8728 …{ 1162 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feat…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1186 arm_smuadx, // llvm.arm.smuadx
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| D | IntrinsicImpl.inc | 1212 "llvm.arm.smuadx",
10090 1, // llvm.arm.smuadx
|