| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 36 define i32 @smulwb(i32 %a, i32 %b) {
37 ; CHECK-LABEL: smulwb
38 ; CHECK: smulwb r0, r0, r1
39 %tmp = call i32 @llvm.arm.smulwb(i32 %a, i32 %b)
101 declare i32 @llvm.arm.smulwb(i32 %a, i32 %b) nounwind readnone
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| D | smul.ll | 120 ; CHECK: smulwb r0, r0, r1
121 ; CHECK-THUMBV6-NOT: smulwb
135 ; CHECK: smulwb r0, r0, r1
136 ; CHECK-THUMBV6-NOT: smulwb
270 ; CHECK: smulwb r0, r0, r1
271 ; CHECK-THUMBV6-NOT: smulwb
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| /external/llvm/test/CodeGen/ARM/ |
| D | smul.ll | 109 ; CHECK: smulwb
122 ; CHECK: smulwb
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| /external/arm-neon-tests/ |
| D | ref_dsp.c | 391 sres = smulwb(svar1, svar2); in exec_dsp()
398 sres = smulwb(svar1, svar2); in exec_dsp()
|
| D | ref-rvct-all.txt | 8034 smulwb(0x12345678, 0x12345678) = 0x6261d94
8036 smulwb(0xf123f456, 0xf123f456) = 0xad52a0
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 75 M(smulwb) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 74 M(smulwb) \
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 709 0xa9,0x00,0x23,0xe1 = smulwb r3, r9, r0
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| D | basic-thumb2-instructions.s.cs | 791 0x39,0xfb,0x00,0xf3 = smulwb r3, r9, r0
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1810 smulwb r3, r9, r0
1813 @ CHECK: smulwb r3, r9, r0 @ encoding: [0xa9,0x00,0x23,0xe1]
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| D | basic-thumb2-instructions.s | 2068 smulwb r3, r9, r0
2074 @ CHECK: smulwb r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3231 void smulwb(Condition cond, Register rd, Register rn, Register rm);
3232 void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); } in smulwb() function
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| D | disasm-aarch32.h | 1179 void smulwb(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2846 void Disassembler::smulwb(Condition cond, in smulwb() function in vixl::aarch32::Disassembler
22204 smulwb(CurrentCond(), in DecodeT32()
56529 smulwb(condition, in DecodeA32()
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| D | assembler-aarch32.cc | 10665 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) { in smulwb() function in vixl::aarch32::Assembler
10685 Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm); in smulwb()
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| D | macro-assembler-aarch32.h | 4065 smulwb(cond, rd, rn, rm); in Smulwb()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2551 smulwb r3, r9, r0
2557 @ CHECK: smulwb r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3]
|
| D | basic-arm-instructions.s | 2585 smulwb r3, r9, r0
2588 @ CHECK: smulwb r3, r9, r0 @ encoding: [0xa9,0x00,0x23,0xe1]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2583 smulwb r3, r9, r0
2586 @ CHECK: smulwb r3, r9, r0 @ encoding: [0xa9,0x00,0x23,0xe1]
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| D | basic-thumb2-instructions.s | 2503 smulwb r3, r9, r0
2509 @ CHECK: smulwb r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1639 # CHECK: smulwb r3, r9, r0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1791 # CHECK: smulwb r3, r9, r0
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1791 # CHECK: smulwb r3, r9, r0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2732 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7758 "smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smu"
8740 …{ 1203 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2…
8741 …{ 1203 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feat…
|