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Searched refs:smusd (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dacle-intrinsics.ll410 define i32 @smusd(i32 %a, i32 %b) nounwind {
411 ; CHECK-LABEL: smusd
412 ; CHECK: smusd r0, r0, r1
413 %tmp = call i32 @llvm.arm.smusd(i32 %a, i32 %b)
480 declare i32 @llvm.arm.smusd(i32, i32) nounwind
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-a32.cc77 M(smusd) \
Dtest-assembler-cond-rd-rn-rm-t32.cc76 M(smusd) \
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs711 0x50,0xf1,0x03,0xe7 = smusd r3, r0, r1
Dbasic-thumb2-instructions.s.cs796 0x40,0xfb,0x01,0xf3 = smusd r3, r0, r1
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1820 smusd r3, r0, r1
1825 @ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7]
Dbasic-thumb2-instructions.s2084 smusd r3, r0, r1
2090 @ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3]
/external/vixl/src/aarch32/
Dassembler-aarch32.h3237 void smusd(Condition cond, Register rd, Register rn, Register rm);
3238 void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); } in smusd() function
Ddisasm-aarch32.h1183 void smusd(Condition cond, Register rd, Register rn, Register rm);
Ddisasm-aarch32.cc2872 void Disassembler::smusd(Condition cond, in smusd() function in vixl::aarch32::Disassembler
21957 smusd(CurrentCond(), in DecodeT32()
63840 smusd(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
Dassembler-aarch32.cc10711 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) { in smusd() function in vixl::aarch32::Assembler
10731 Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm); in smusd()
Dmacro-assembler-aarch32.h4089 smusd(cond, rd, rn, rm); in Smusd()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s2567 smusd r3, r0, r1
2573 @ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3]
Dbasic-arm-instructions.s2595 smusd r3, r0, r1
2600 @ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s2593 smusd r3, r0, r1
2598 @ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7]
Dbasic-thumb2-instructions.s2519 smusd r3, r0, r1
2525 @ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1649 # CHECK: smusd r3, r0, r1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1801 # CHECK: smusd r3, r0, r1
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1801 # CHECK: smusd r3, r0, r1
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td2636 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2843 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>;
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2864 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7758 "smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smu"
8744 …{ 1217 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F…
8745 …{ 1217 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Featur…
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1193 arm_smusd, // llvm.arm.smusd
DIntrinsicImpl.inc1219 "llvm.arm.smusd",
10097 1, // llvm.arm.smusd