/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | acle-intrinsics.ll | 410 define i32 @smusd(i32 %a, i32 %b) nounwind { 411 ; CHECK-LABEL: smusd 412 ; CHECK: smusd r0, r0, r1 413 %tmp = call i32 @llvm.arm.smusd(i32 %a, i32 %b) 480 declare i32 @llvm.arm.smusd(i32, i32) nounwind
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/external/vixl/test/aarch32/ |
D | test-assembler-cond-rd-rn-rm-a32.cc | 77 M(smusd) \
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D | test-assembler-cond-rd-rn-rm-t32.cc | 76 M(smusd) \
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/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 711 0x50,0xf1,0x03,0xe7 = smusd r3, r0, r1
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D | basic-thumb2-instructions.s.cs | 796 0x40,0xfb,0x01,0xf3 = smusd r3, r0, r1
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 1820 smusd r3, r0, r1 1825 @ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7]
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D | basic-thumb2-instructions.s | 2084 smusd r3, r0, r1 2090 @ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3237 void smusd(Condition cond, Register rd, Register rn, Register rm); 3238 void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); } in smusd() function
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D | disasm-aarch32.h | 1183 void smusd(Condition cond, Register rd, Register rn, Register rm);
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D | disasm-aarch32.cc | 2872 void Disassembler::smusd(Condition cond, in smusd() function in vixl::aarch32::Disassembler 21957 smusd(CurrentCond(), in DecodeT32() 63840 smusd(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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D | assembler-aarch32.cc | 10711 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) { in smusd() function in vixl::aarch32::Assembler 10731 Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm); in smusd()
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D | macro-assembler-aarch32.h | 4089 smusd(cond, rd, rn, rm); in Smusd()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | basic-thumb2-instructions.s | 2567 smusd r3, r0, r1 2573 @ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3]
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D | basic-arm-instructions.s | 2595 smusd r3, r0, r1 2600 @ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7]
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/external/llvm/test/MC/ARM/ |
D | basic-arm-instructions.s | 2593 smusd r3, r0, r1 2598 @ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7]
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D | basic-thumb2-instructions.s | 2519 smusd r3, r0, r1 2525 @ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3]
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1649 # CHECK: smusd r3, r0, r1
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1801 # CHECK: smusd r3, r0, r1
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/external/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1801 # CHECK: smusd r3, r0, r1
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2636 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2843 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>;
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2864 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 7758 "smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smu" 8744 …{ 1217 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F… 8745 …{ 1217 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Featur…
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/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
D | IntrinsicEnums.inc | 1193 arm_smusd, // llvm.arm.smusd
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D | IntrinsicImpl.inc | 1219 "llvm.arm.smusd", 10097 1, // llvm.arm.smusd
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