| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 417 define i32 @smusdx(i32 %a, i32 %b) nounwind {
418 ; CHECK-LABEL: smusdx
419 ; CHECK: smusdx r0, r0, r1
420 %tmp = call i32 @llvm.arm.smusdx(i32 %a, i32 %b)
481 declare i32 @llvm.arm.smusdx(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 78 M(smusdx) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 77 M(smusdx) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 712 0x79,0xf2,0x03,0xe7 = smusdx r3, r9, r2
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| D | basic-thumb2-instructions.s.cs | 797 0x49,0xfb,0x12,0xf3 = smusdx r3, r9, r2
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1821 smusdx r3, r9, r2
1826 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x79,0xf2,0x03,0xe7]
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| D | basic-thumb2-instructions.s | 2085 smusdx r3, r9, r2
2091 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x49,0xfb,0x12,0xf3]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3240 void smusdx(Condition cond, Register rd, Register rn, Register rm);
3241 void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); } in smusdx() function
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| D | disasm-aarch32.h | 1185 void smusdx(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2885 void Disassembler::smusdx(Condition cond, in smusdx() function in vixl::aarch32::Disassembler
21992 smusdx(CurrentCond(), in DecodeT32()
63879 smusdx(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 10734 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) { in smusdx() function in vixl::aarch32::Assembler
10754 Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm); in smusdx()
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| D | macro-assembler-aarch32.h | 4101 smusdx(cond, rd, rn, rm); in Smusdx()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2568 smusdx r3, r9, r2
2574 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x49,0xfb,0x12,0xf3]
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| D | basic-arm-instructions.s | 2596 smusdx r3, r9, r2
2601 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x79,0xf2,0x03,0xe7]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2594 smusdx r3, r9, r2
2599 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x79,0xf2,0x03,0xe7]
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| D | basic-thumb2-instructions.s | 2520 smusdx r3, r9, r2
2526 @ CHECK: smusdx r3, r9, r2 @ encoding: [0x49,0xfb,0x12,0xf3]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1650 # CHECK: smusdx r3, r9, r2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1802 # CHECK: smusdx r3, r9, r2
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1802 # CHECK: smusdx r3, r9, r2
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2642 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2844 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2870 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 8746 …{ 1223 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2…
8747 …{ 1223 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feat…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 1194 arm_smusdx, // llvm.arm.smusdx
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| D | IntrinsicImpl.inc | 1220 "llvm.arm.smusdx",
10098 1, // llvm.arm.smusdx
|