Searched refs:spu (Results 1 – 25 of 82) sorted by relevance
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| /external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/ |
| D | intrinsics_logical.ll | 5 target triple = "spu"
7 declare <4 x i32> @llvm.spu.si.and(<4 x i32>, <4 x i32>)
8 declare <4 x i32> @llvm.spu.si.andc(<4 x i32>, <4 x i32>)
9 declare <4 x i32> @llvm.spu.si.andi(<4 x i32>, i16)
10 declare <8 x i16> @llvm.spu.si.andhi(<8 x i16>, i16)
11 declare <16 x i8> @llvm.spu.si.andbi(<16 x i8>, i8)
13 declare <4 x i32> @llvm.spu.si.or(<4 x i32>, <4 x i32>)
14 declare <4 x i32> @llvm.spu.si.orc(<4 x i32>, <4 x i32>)
15 declare <4 x i32> @llvm.spu.si.ori(<4 x i32>, i16)
16 declare <8 x i16> @llvm.spu.si.orhi(<8 x i16>, i16)
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| D | intrinsics_branch.ll | 11 target triple = "spu"
13 declare <4 x i32> @llvm.spu.si.shli(<4 x i32>, i8)
15 declare <4 x i32> @llvm.spu.si.ceq(<4 x i32>, <4 x i32>)
16 declare <16 x i8> @llvm.spu.si.ceqb(<16 x i8>, <16 x i8>)
17 declare <8 x i16> @llvm.spu.si.ceqh(<8 x i16>, <8 x i16>)
18 declare <4 x i32> @llvm.spu.si.ceqi(<4 x i32>, i16)
19 declare <8 x i16> @llvm.spu.si.ceqhi(<8 x i16>, i16)
20 declare <16 x i8> @llvm.spu.si.ceqbi(<16 x i8>, i8)
22 declare <4 x i32> @llvm.spu.si.cgt(<4 x i32>, <4 x i32>)
23 declare <16 x i8> @llvm.spu.si.cgtb(<16 x i8>, <16 x i8>)
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| D | intrinsics_float.ll | 13 target triple = "spu"
15 declare <4 x i32> @llvm.spu.si.shli(<4 x i32>, i8)
17 declare <4 x float> @llvm.spu.si.fa(<4 x float>, <4 x float>)
18 declare <4 x float> @llvm.spu.si.fs(<4 x float>, <4 x float>)
19 declare <4 x float> @llvm.spu.si.fm(<4 x float>, <4 x float>)
21 declare <4 x float> @llvm.spu.si.fceq(<4 x float>, <4 x float>)
22 declare <4 x float> @llvm.spu.si.fcmeq(<4 x float>, <4 x float>)
23 declare <4 x float> @llvm.spu.si.fcgt(<4 x float>, <4 x float>)
24 declare <4 x float> @llvm.spu.si.fcmgt(<4 x float>, <4 x float>)
26 declare <4 x float> @llvm.spu.si.fma(<4 x float>, <4 x float>, <4 x float>)
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| D | i8ops.ll | 5 target triple = "spu"
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| D | fdiv.ll | 12 target triple = "spu"
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| D | immed16.ll | 4 target triple = "spu"
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| D | 2009-01-01-BrCond.ll | 5 target triple = "spu"
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| D | ctpop.ll | 7 target triple = "spu"
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| D | fneg-fabs.ll | 7 target triple = "spu"
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| D | int2fp.ll | 11 target triple = "spu"
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| D | call.ll | 8 target triple = "spu"
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| D | sext128.ll | 5 target triple = "spu"
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| D | i64ops.ll | 17 target triple = "spu"
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| D | loads.ll | 5 target triple = "spu"
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| D | immed64.ll | 18 target triple = "spu"
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| D | immed32.ll | 17 target triple = "spu"
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 32 to add 'spu' to configure's --enable-targets option, e.g.:
35 --enable-targets=x86,x86_64,powerpc,spu
89 * spu.h instrinsics added but not tested. Need to have an operational
90 llvm-spu-gcc in order to write a unit test harness.
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| /external/swiftshader/third_party/LLVM/include/llvm/ |
| D | IntrinsicsCellSPU.td | 101 // All Cell SPU intrinsics start with "llvm.spu.".
102 let TargetPrefix = "spu" in {
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| /external/libxkbcommon/xkbcommon/build-aux/ |
| D | config.sub | 309 | spu \
1534 spu-*)
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| /external/python/cpython2/Modules/_ctypes/libffi/ |
| D | config.sub | 309 | spu \
1534 spu-*)
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| /external/google-breakpad/autotools/ |
| D | config.sub | 311 | spu \
1562 spu-*)
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| /external/libnetfilter_conntrack/build-aux/ |
| D | config.sub | 312 | spu \
1545 spu-*)
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| /external/speex/ |
| D | config.sub | 311 | spu \
1540 spu-*)
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| /external/iperf3/config/ |
| D | config.sub | 310 | spu \
1536 spu-*)
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| /external/libcap-ng/libcap-ng-0.7/ |
| D | config.sub | 304 | spu \
1518 spu-*)
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