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Searched refs:sqdmull (Results 1 – 25 of 64) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s6 sqdmull s1, h1, v1.h[1]
7 sqdmull s8, h2, v5.h[2]
8 sqdmull s12, h17, v9.h[3]
9 sqdmull s31, h31, v15.h[7]
10 sqdmull d1, s1, v4.s[0] define
11 sqdmull d31, s31, v31.s[3]
12 sqdmull d9, s10, v15.s[0] define
Dneon-scalar-mul.s61 sqdmull s12, h22, h12
62 sqdmull d15, s22, s12
Dneon-2velem.s247 sqdmull v0.4s, v1.4h, v2.h[2]
248 sqdmull v0.2d, v1.2s, v2.s[2]
249 sqdmull v0.2d, v1.2s, v22.s[2]
Dneon-diagnostics.s2519 sqdmull v0.4s, v1.4s, v2.4h
2520 sqdmull v0.2d, v1.2d, v2.2s
2538 sqdmull v0.8h, v1.8b, v2.8b
3523 sqdmull v0.4h, v1.4h, v2.h[2]
3524 sqdmull v0.4s, v1.4h, v2.h[8]
3525 sqdmull v0.4s, v1.4h, v16.h[4]
3526 sqdmull v0.2s, v1.2s, v2.s[2]
3527 sqdmull v0.2d, v1.2s, v2.s[4]
3528 sqdmull v0.2d, v1.2s, v22.s[4]
4779 sqdmull s12, h22, s12
[all …]
Darm64-advsimd.s1147 sqdmull.h s0, h0, v0[7]
1148 sqdmull.s d0, s0, v0[3]
1165 ; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f]
1166 ; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f]
1253 sqdmull.4s v0, v0, v0[0]
1255 sqdmull.2d v0, v0, v0[2]
1322 ; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f]
1324 ; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f]
1985 sqdmull s0, h0, h0
1986 sqdmull d0, s0, s0 define
[all …]
Dneon-3vdiff.s269 sqdmull v0.4s, v1.4h, v2.4h
270 sqdmull v0.2d, v1.2s, v2.2s
/external/llvm/test/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s6 sqdmull s1, h1, v1.h[1]
7 sqdmull s8, h2, v5.h[2]
8 sqdmull s12, h17, v9.h[3]
9 sqdmull s31, h31, v15.h[7]
10 sqdmull d1, s1, v4.s[0] define
11 sqdmull d31, s31, v31.s[3]
12 sqdmull d9, s10, v15.s[0] define
Dneon-scalar-mul.s61 sqdmull s12, h22, h12
62 sqdmull d15, s22, s12
Dneon-2velem.s247 sqdmull v0.4s, v1.4h, v2.h[2]
248 sqdmull v0.2d, v1.2s, v2.s[2]
249 sqdmull v0.2d, v1.2s, v22.s[2]
Dneon-diagnostics.s2558 sqdmull v0.4s, v1.4s, v2.4h
2559 sqdmull v0.2d, v1.2d, v2.2s
2579 sqdmull v0.8h, v1.8b, v2.8b
3583 sqdmull v0.4h, v1.4h, v2.h[2]
3584 sqdmull v0.4s, v1.4h, v2.h[8]
3585 sqdmull v0.4s, v1.4h, v16.h[4]
3586 sqdmull v0.2s, v1.2s, v2.s[2]
3587 sqdmull v0.2d, v1.2s, v2.s[4]
3588 sqdmull v0.2d, v1.2s, v22.s[4]
4839 sqdmull s12, h22, s12
[all …]
Darm64-advsimd.s1147 sqdmull.h s0, h0, v0[7]
1148 sqdmull.s d0, s0, v0[3]
1165 ; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f]
1166 ; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f]
1253 sqdmull.4s v0, v0, v0[0]
1255 sqdmull.2d v0, v0, v0[2]
1322 ; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f]
1324 ; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f]
1985 sqdmull s0, h0, h0
1986 sqdmull d0, s0, s0 define
[all …]
Dneon-3vdiff.s269 sqdmull v0.4s, v1.4h, v2.4h
270 sqdmull v0.2d, v1.2s, v2.2s
/external/capstone/suite/MC/AArch64/
Dneon-scalar-by-elem-saturating-mul.s.cs2 0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1]
3 0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2]
4 0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3]
5 0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7]
6 0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0]
7 0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3]
8 0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0]
Dneon-scalar-mul.s.cs12 0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12
13 0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12
Dneon-2velem.s.cs96 0x20,0xb0,0x62,0x0f = sqdmull v0.4s, v1.4h, v2.h[2]
97 0x20,0xb8,0x82,0x0f = sqdmull v0.2d, v1.2s, v2.s[2]
98 0x20,0xb8,0x96,0x0f = sqdmull v0.2d, v1.2s, v22.s[2]
/external/llvm/test/CodeGen/AArch64/
Dmachine-copy-prop.ll32 …%sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i1…
33 …= tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
85 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
Darm64-neon-2velem-high.ll115 …%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
126 …%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
139 …%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
150 …%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
273 …%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
285 …%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
299 …%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
311 …%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
435 …%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
447 …%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
[all …]
Darm64-vmul.ll68 ;CHECK: sqdmull.4s
71 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
77 ;CHECK: sqdmull.2d
80 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
91 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
102 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
107 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
108 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
309 %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
320 %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
Darm64-detect-vec-redux.ll21 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> undef, <2 x i32> unde…
39 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) #1
Darm64-neon-2velem.ll25 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
27 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
1157 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1168 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1180 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1192 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
1203 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1214 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1226 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1238 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dmachine-copy-prop.ll32 …%sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i1…
33 …= tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
85 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
Darm64-vmul.ll68 ;CHECK: sqdmull.4s
71 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
77 ;CHECK: sqdmull.2d
80 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
86 ;CHECK: sqdmull.4s
91 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
97 ;CHECK: sqdmull.2d
102 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
107 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
108 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
[all …]
Darm64-neon-2velem-high.ll115 …%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
126 …%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
139 …%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
150 …%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
273 …%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
285 …%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
299 …%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
311 …%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> …
435 …%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
447 …%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16>…
[all …]
Darm64-detect-vec-redux.ll21 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> undef, <2 x i32> unde…
39 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) #1
Darm64-neon-2velem.ll28 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
30 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
1095 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1105 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1116 …%vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1127 …%vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
1137 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %shuffl…
1147 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %shuffl…
1158 …%vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i, <4 x i16>…
1169 …%vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i, <2 x i32>…
[all …]

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