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Searched refs:sqsub (Results 1 – 25 of 60) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dsqsub.s11 sqsub z0.b, z0.b, z0.b label
17 sqsub z0.h, z0.h, z0.h label
23 sqsub z0.s, z0.s, z0.s label
29 sqsub z0.d, z0.d, z0.d label
35 sqsub z0.b, z0.b, #0 label
41 sqsub z31.b, z31.b, #255 label
47 sqsub z0.h, z0.h, #0 label
53 sqsub z0.h, z0.h, #0, lsl #8 label
59 sqsub z31.h, z31.h, #255, lsl #8 label
65 sqsub z31.h, z31.h, #65280 label
[all …]
Dsqsub-diagnostics.s4 sqsub z22.h, z10.h, z32.h label
10 sqsub z20.h, z2.h, z31.x label
16 sqsub z27.h, z11.h, z27.b label
25 sqsub z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b label
30 sqsub z0.b, z0.b, #-1 label
35 sqsub z0.b, z0.b, #1, lsl #8 label
40 sqsub z0.b, z0.b, #256 label
45 sqsub z0.h, z0.h, #-1 label
50 sqsub z0.h, z0.h, #256, lsl #8 label
55 sqsub z0.h, z0.h, #65536 label
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vqsub.ll5 ;CHECK: sqsub.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ;CHECK: sqsub.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
23 ;CHECK: sqsub.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
59 ;CHECK: sqsub.16b
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
68 ;CHECK: sqsub.8h
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
Darm64-neon-v8.1a.ll22 declare <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>)
23 declare <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>)
24 declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
26 declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)
27 declare i16 @llvm.aarch64.neon.sqsub.i16(i16, i16)
76 %retval = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc, <4 x i16> %prod)
86 %retval = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc, <8 x i16> %prod)
96 %retval = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %acc, <2 x i32> %prod)
106 %retval = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc, <4 x i32> %prod)
[all …]
Darm64-arith-saturating.ll46 ; CHECK: sqsub s0, s0, s1
49 %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
55 ; CHECK: sqsub d0, d0, d1
58 %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
82 declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone
83 declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone
Darm64-vecFold.ll125 …%vqsub2.i = tail call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %a0, <2 x i32> %a1) nounw…
127 ; CHECK: sqsub.2s v0, v0, v1
136 declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
Darm64-neon-2velem-high.ll436 …%vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.…
448 …%vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.…
462 …%vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i…
474 …%vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i…
571 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
572 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
Darm64-vmul.ll300 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
301 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
358 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
369 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
382 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
395 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
1041 %res = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %A, i32 %prod)
1044 declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)
1062 %res = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %A, i64 %prod)
1065 declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64)
[all …]
Darm64-neon-2velem.ll32 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
34 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
1138 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
1148 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
1159 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
1170 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
2455 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
2465 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
2476 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
2487 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
/external/llvm/test/CodeGen/AArch64/
Darm64-vqsub.ll5 ;CHECK: sqsub.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ;CHECK: sqsub.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
23 ;CHECK: sqsub.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
59 ;CHECK: sqsub.16b
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
68 ;CHECK: sqsub.8h
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
[all …]
Darm64-neon-v8.1a.ll19 declare <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>)
20 declare <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>)
21 declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>)
22 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
23 declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)
24 declare i16 @llvm.aarch64.neon.sqsub.i16(i16, i16)
73 %retval = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc, <4 x i16> %prod)
83 %retval = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc, <8 x i16> %prod)
93 %retval = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %acc, <2 x i32> %prod)
103 %retval = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc, <4 x i32> %prod)
[all …]
Darm64-arith-saturating.ll46 ; CHECK: sqsub s0, s0, s1
49 %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
55 ; CHECK: sqsub d0, d0, d1
58 %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
82 declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64) nounwind readnone
83 declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) nounwind readnone
Darm64-vecFold.ll125 …%vqsub2.i = tail call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %a0, <2 x i32> %a1) nounw…
127 ; CHECK: sqsub.2s v0, v0, v1
136 declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
Darm64-neon-2velem-high.ll436 …%vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.…
448 …%vqdmlsl17.i.i = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.…
462 …%vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i…
474 …%vqdmlsl11.i.i = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i…
571 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
572 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
Darm64-vmul.ll300 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
301 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
358 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
369 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
382 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
395 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
1041 %res = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %A, i32 %prod)
1044 declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)
1062 %res = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %A, i64 %prod)
1065 declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64)
[all …]
Darm64-neon-2velem.ll29 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
31 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
1204 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
1215 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
1227 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
1239 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
2583 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
2594 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
2606 …%vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2…
2618 …%vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2…
/external/llvm/test/MC/AArch64/
Dneon-saturating-add-sub.s47 sqsub v0.8b, v1.8b, v2.8b
48 sqsub v0.16b, v1.16b, v2.16b
49 sqsub v0.4h, v1.4h, v2.4h
50 sqsub v0.8h, v1.8h, v2.8h
51 sqsub v0.2s, v1.2s, v2.2s
52 sqsub v0.4s, v1.4s, v2.4s
53 sqsub v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s32 sqsub b0, b1, b2
33 sqsub h10, h11, h12
34 sqsub s20, s21, s2
35 sqsub d17, d31, d8
/external/capstone/suite/MC/AArch64/
Dneon-saturating-add-sub.s.cs16 0x20,0x2c,0x22,0x0e = sqsub v0.8b, v1.8b, v2.8b
17 0x20,0x2c,0x22,0x4e = sqsub v0.16b, v1.16b, v2.16b
18 0x20,0x2c,0x62,0x0e = sqsub v0.4h, v1.4h, v2.4h
19 0x20,0x2c,0x62,0x4e = sqsub v0.8h, v1.8h, v2.8h
20 0x20,0x2c,0xa2,0x0e = sqsub v0.2s, v1.2s, v2.2s
21 0x20,0x2c,0xa2,0x4e = sqsub v0.4s, v1.4s, v2.4s
22 0x20,0x2c,0xe2,0x4e = sqsub v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s.cs10 0x20,0x2c,0x22,0x5e = sqsub b0, b1, b2
11 0x6a,0x2d,0x6c,0x5e = sqsub h10, h11, h12
12 0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2
13 0xf1,0x2f,0xe8,0x5e = sqsub d17, d31, d8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-saturating-add-sub.s47 sqsub v0.8b, v1.8b, v2.8b
48 sqsub v0.16b, v1.16b, v2.16b
49 sqsub v0.4h, v1.4h, v2.4h
50 sqsub v0.8h, v1.8h, v2.8h
51 sqsub v0.2s, v1.2s, v2.2s
52 sqsub v0.4s, v1.4s, v2.4s
53 sqsub v0.2d, v1.2d, v2.2d
Dneon-scalar-saturating-add-sub.s32 sqsub b0, b1, b2
33 sqsub h10, h11, h12
34 sqsub s20, s21, s2
35 sqsub d17, d31, d8
/external/vixl/test/test-trace-reference/
Dlog-disasm1451 0x~~~~~~~~~~~~~~~~ 5e2b2fb3 sqsub b19, b29, b11
1452 0x~~~~~~~~~~~~~~~~ 5ee62ff5 sqsub d21, d31, d6
1453 0x~~~~~~~~~~~~~~~~ 5e732d52 sqsub h18, h10, h19
1454 0x~~~~~~~~~~~~~~~~ 5ea02ca6 sqsub s6, s5, s0
1455 0x~~~~~~~~~~~~~~~~ 4e202ed5 sqsub v21.16b, v22.16b, v0.16b
1456 0x~~~~~~~~~~~~~~~~ 4ef12d56 sqsub v22.2d, v10.2d, v17.2d
1457 0x~~~~~~~~~~~~~~~~ 0ea22ea8 sqsub v8.2s, v21.2s, v2.2s
1458 0x~~~~~~~~~~~~~~~~ 0e7b2f32 sqsub v18.4h, v25.4h, v27.4h
1459 0x~~~~~~~~~~~~~~~~ 4ea62c6d sqsub v13.4s, v3.4s, v6.4s
1460 0x~~~~~~~~~~~~~~~~ 0e302fbc sqsub v28.8b, v29.8b, v16.8b
[all …]
Dlog-disasm-colour1451 0x~~~~~~~~~~~~~~~~ 5e2b2fb3 sqsub b19, b29, b11
1452 0x~~~~~~~~~~~~~~~~ 5ee62ff5 sqsub d21, d31, d6
1453 0x~~~~~~~~~~~~~~~~ 5e732d52 sqsub h18, h10, h19
1454 0x~~~~~~~~~~~~~~~~ 5ea02ca6 sqsub s6, s5, s0
1455 0x~~~~~~~~~~~~~~~~ 4e202ed5 sqsub v21.16b, v22.16b, v0.16b
1456 0x~~~~~~~~~~~~~~~~ 4ef12d56 sqsub v22.2d, v10.2d, v17.2d
1457 0x~~~~~~~~~~~~~~~~ 0ea22ea8 sqsub v8.2s, v21.2s, v2.2s
1458 0x~~~~~~~~~~~~~~~~ 0e7b2f32 sqsub v18.4h, v25.4h, v27.4h
1459 0x~~~~~~~~~~~~~~~~ 4ea62c6d sqsub v13.4s, v3.4s, v6.4s
1460 0x~~~~~~~~~~~~~~~~ 0e302fbc sqsub v28.8b, v29.8b, v16.8b
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1684 __ sqsub(b19, b29, b11); in GenerateTestSequenceNEON() local
1685 __ sqsub(d21, d31, d6); in GenerateTestSequenceNEON() local
1686 __ sqsub(h18, h10, h19); in GenerateTestSequenceNEON() local
1687 __ sqsub(s6, s5, s0); in GenerateTestSequenceNEON() local
1688 __ sqsub(v21.V16B(), v22.V16B(), v0.V16B()); in GenerateTestSequenceNEON() local
1689 __ sqsub(v22.V2D(), v10.V2D(), v17.V2D()); in GenerateTestSequenceNEON() local
1690 __ sqsub(v8.V2S(), v21.V2S(), v2.V2S()); in GenerateTestSequenceNEON() local
1691 __ sqsub(v18.V4H(), v25.V4H(), v27.V4H()); in GenerateTestSequenceNEON() local
1692 __ sqsub(v13.V4S(), v3.V4S(), v6.V4S()); in GenerateTestSequenceNEON() local
1693 __ sqsub(v28.V8B(), v29.V8B(), v16.V8B()); in GenerateTestSequenceNEON() local
[all …]

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