| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 242 define i32 @ssax(i32 %a, i32 %b) nounwind {
243 ; CHECK-LABEL: ssax
244 ; CHECK: ssax r0, r0, r1
245 %tmp = call i32 @llvm.arm.ssax(i32 %a, i32 %b)
456 declare i32 @llvm.arm.ssax(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 97 M(ssax) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 96 M(ssax) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 827 0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4
830 0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4
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| D | basic-arm-instructions.s.cs | 758 0x54,0x2f,0x13,0xe6 = ssax r2, r3, r4
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2157 ssax r2, r3, r4
2161 @ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
2164 @ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
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| D | basic-arm-instructions.s | 1910 ssax r2, r3, r4
1913 @ CHECK: ssax r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xe6]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2666 ssax r2, r3, r4
2670 @ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
2673 @ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
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| D | basic-arm-instructions.s | 2728 ssax r2, r3, r4
2731 @ CHECK: ssax r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xe6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2618 ssax r2, r3, r4
2622 @ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
2625 @ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2]
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| D | basic-arm-instructions.s | 2726 ssax r2, r3, r4
2729 @ CHECK: ssax r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xe6]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3253 void ssax(Condition cond, Register rd, Register rn, Register rm);
3254 void ssax(Register rd, Register rn, Register rm) { ssax(al, rd, rn, rm); } in ssax() function
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| D | disasm-aarch32.h | 1191 void ssax(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2916 void Disassembler::ssax(Condition cond, Register rd, Register rn, Register rm) { in ssax() function in vixl::aarch32::Disassembler
21463 ssax(CurrentCond(), in DecodeT32()
62348 ssax(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 10842 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) { in ssax() function in vixl::aarch32::Assembler
10862 Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm); in ssax()
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1737 # CHECK: ssax r2, r3, r4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1889 # CHECK: ssax r2, r3, r4
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1889 # CHECK: ssax r2, r3, r4
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3191 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
4981 def : MnemonicAlias<"ssubaddx", "ssax">;
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| D | ARMInstrThumb2.td | 1958 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3737 def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>;
5991 def : MnemonicAlias<"ssubaddx", "ssax">;
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| D | ARMInstrThumb2.td | 2231 def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3592 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
5691 def : MnemonicAlias<"ssubaddx", "ssax">;
|
| D | ARMInstrThumb2.td | 2163 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1320 Mnemonic = "ssax"; // "ssubaddx"
7759 "sdx\005srsda\005srsdb\005srsia\005srsib\004ssat\006ssat16\004ssax\006ss"
8778 …{ 1266 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Fea…
8779 …{ 1266 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_C…
|