| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 249 define i32 @ssub16(i32 %a, i32 %b) nounwind {
250 ; CHECK-LABEL: ssub16
251 ; CHECK: ssub16 r0, r0, r1
252 %tmp = call i32 @llvm.arm.ssub16(i32 %a, i32 %b)
457 declare i32 @llvm.arm.ssub16(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 98 M(ssub16) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 97 M(ssub16) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 760 0x76,0x1f,0x10,0xe6 = ssub16 r1, r0, r6
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| D | basic-thumb2-instructions.s.cs | 833 0xd0,0xfa,0x06,0xf1 = ssub16 r1, r0, r6
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1919 ssub16 r1, r0, r6
1924 @ CHECK: ssub16 r1, r0, r6 @ encoding: [0x76,0x1f,0x10,0xe6]
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| D | basic-thumb2-instructions.s | 2172 ssub16 r1, r0, r6
2178 @ CHECK: ssub16 r1, r0, r6 @ encoding: [0xd0,0xfa,0x06,0xf1]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3256 void ssub16(Condition cond, Register rd, Register rn, Register rm);
3257 void ssub16(Register rd, Register rn, Register rm) { ssub16(al, rd, rn, rm); } in ssub16() function
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| D | disasm-aarch32.h | 1193 void ssub16(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2926 void Disassembler::ssub16(Condition cond, in ssub16() function in vixl::aarch32::Disassembler
21706 ssub16(CurrentCond(), in DecodeT32()
62371 ssub16(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 10865 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) { in ssub16() function in vixl::aarch32::Assembler
10885 Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm); in ssub16()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2681 ssub16 r1, r0, r6
2687 @ CHECK: ssub16 r1, r0, r6 @ encoding: [0xd0,0xfa,0x06,0xf1]
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| D | basic-arm-instructions.s | 2737 ssub16 r1, r0, r6
2742 @ CHECK: ssub16 r1, r0, r6 @ encoding: [0x76,0x1f,0x10,0xe6]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2735 ssub16 r1, r0, r6
2740 @ CHECK: ssub16 r1, r0, r6 @ encoding: [0x76,0x1f,0x10,0xe6]
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| D | basic-thumb2-instructions.s | 2633 ssub16 r1, r0, r6
2639 @ CHECK: ssub16 r1, r0, r6 @ encoding: [0xd0,0xfa,0x06,0xf1]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1746 # CHECK: ssub16 r1, r0, r6
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1898 # CHECK: ssub16 r1, r0, r6
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1898 # CHECK: ssub16 r1, r0, r6
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1959 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
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| D | ARMInstrInfo.td | 3192 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2232 def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;
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| D | ARMInstrInfo.td | 3738 def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2164 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
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| D | ARMInstrInfo.td | 3593 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 8780 …{ 1271 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2…
8781 …{ 1271 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { M…
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