| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 114 define i32 @ssub8(i32 %a, i32 %b) nounwind {
115 ; CHECK-LABEL: ssub8
116 ; CHECK: ssub8 r0, r0, r1
117 %tmp = call i32 @llvm.arm.ssub8(i32 %a, i32 %b)
437 declare i32 @llvm.arm.ssub8(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 99 M(ssub8) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 98 M(ssub8) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 762 0xf4,0x9f,0x12,0xe6 = ssub8 r9, r2, r4
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| D | basic-thumb2-instructions.s.cs | 834 0xc2,0xfa,0x04,0xf9 = ssub8 r9, r2, r4
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1921 ssub8 r9, r2, r4
1926 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6]
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| D | basic-thumb2-instructions.s | 2173 ssub8 r9, r2, r4
2179 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xc2,0xfa,0x04,0xf9]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3259 void ssub8(Condition cond, Register rd, Register rn, Register rm);
3260 void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); } in ssub8() function
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| D | disasm-aarch32.h | 1195 void ssub8(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2939 void Disassembler::ssub8(Condition cond, in ssub8() function in vixl::aarch32::Disassembler
21355 ssub8(CurrentCond(), in DecodeT32()
62388 ssub8(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 10888 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) { in ssub8() function in vixl::aarch32::Assembler
10908 Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm); in ssub8()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2682 ssub8 r9, r2, r4
2688 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xc2,0xfa,0x04,0xf9]
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| D | basic-arm-instructions.s | 2739 ssub8 r9, r2, r4
2744 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2737 ssub8 r9, r2, r4
2742 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6]
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| D | basic-thumb2-instructions.s | 2634 ssub8 r9, r2, r4
2640 @ CHECK: ssub8 r9, r2, r4 @ encoding: [0xc2,0xfa,0x04,0xf9]
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1748 # CHECK: ssub8 r9, r2, r4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1900 # CHECK: ssub8 r9, r2, r4
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1900 # CHECK: ssub8 r9, r2, r4
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1960 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
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| D | ARMInstrInfo.td | 3193 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2233 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
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| D | ARMInstrInfo.td | 3739 def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2165 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
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| D | ARMInstrInfo.td | 3594 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7760 "ub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006"
8782 …{ 1278 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F…
8783 …{ 1278 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK…
|