| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | thumbv8m.s | 112 stlb r1, [r3] label
|
| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 41 stlb r2, [r1]
44 @ CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | thumbv8m.s | 112 stlb r1, [r3] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s.cs | 14 0xc1,0xe8,0x8f,0x2f = stlb r2, [r1]
|
| D | load-store-acquire-release-v8.s.cs | 14 0x92,0xfc,0xc1,0xe1 = stlb r2, [r1]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 32 # CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | load-store-acquire-release-v8.txt | 31 # CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 32 # CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
|
| D | load-store-acquire-release-v8.txt | 31 # CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | atomic-ops-v8.ll | 1320 ; CHECK: stlb r0, [r[[ADDR]]]
1337 ; CHECK: stlb r0, [r[[ADDR]]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | atomic-ops-v8.ll | 1323 ; CHECK: stlb r0, [r[[ADDR]]]
1340 ; CHECK: stlb r0, [r[[ADDR]]]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3265 void stlb(Condition cond, Register rt, const MemOperand& operand);
3266 void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); } in stlb() function
|
| D | disasm-aarch32.h | 1199 void stlb(Condition cond, Register rt, const MemOperand& operand);
|
| D | disasm-aarch32.cc | 2958 void Disassembler::stlb(Condition cond, in stlb() function in vixl::aarch32::Disassembler
10044 stlb(CurrentCond(), in DecodeT32()
58017 stlb(condition, in DecodeA32()
|
| D | assembler-aarch32.cc | 10937 void Assembler::stlb(Condition cond, Register rt, const MemOperand& operand) { in stlb() function in vixl::aarch32::Assembler
10960 Delegate(kStlb, &Assembler::stlb, cond, rt, operand); in stlb()
|
| D | macro-assembler-aarch32.h | 4185 stlb(cond, rt, operand); in Stlb()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1611 "stlb", "\t$Rt, $addr", []>;
|
| D | ARMInstrInfo.td | 3228 NoItinerary, "stlb", "\t$Rt, $addr", []>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1605 "stlb", "\t$Rt, $addr", []>;
|
| D | ARMInstrInfo.td | 3118 NoItinerary, "stlb", "\t$Rt, $addr", []>;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7760 "ub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006"
8818 …{ 1308 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feat…
8819 …{ 1308 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_…
|