| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 21 ; CHECK: stlexd
27 %stlexd = tail call i32 @llvm.arm.stlexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
28 ret i32 %stlexd
32 declare i32 @llvm.arm.stlexd(i32, i32, i8*) nounwind
|
| D | atomic-ops-v8.ll | 192 ; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
384 ; CHECK: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
681 ; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
682 ; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
907 ; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
908 ; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
1020 ; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
1021 ; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
1394 ; CHECK: stlexd [[STATUS:r[0-9]+]], r0, r1, {{.*}}[[ADDR]]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 21 ; CHECK: stlexd
27 %stlexd = tail call i32 @llvm.arm.stlexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
28 ret i32 %stlexd
32 declare i32 @llvm.arm.stlexd(i32, i32, i8*) nounwind
|
| D | atomic-ops-v8.ll | 192 ; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
384 ; CHECK: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
681 ; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
682 ; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
907 ; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
908 ; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
1020 ; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
1021 ; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
1391 ; CHECK: stlexd [[STATUS:r[0-9]+]], r0, r1, {{.*}}[[ADDR]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 20 stlexd r6, r2, r3, [r8]
24 @ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 20 stlexd r6, r2, r3, [r8]
24 @ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23]
|
| D | thumbv8m.s | 139 stlexd r0, r1, r2, [r2] label
|
| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 20 stlexd r6, r2, r3, [r8]
24 @ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 20 stlexd r6, r2, r3, [r8]
24 @ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23]
|
| D | thumbv8m.s | 139 stlexd r0, r1, r2, [r2] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s.cs | 9 0xc8,0xe8,0xf6,0x23 = stlexd r6, r2, r3, [r8]
|
| D | load-store-acquire-release-v8.s.cs | 9 0x92,0x6e,0xa8,0xe1 = stlexd r6, r2, r3, [r8]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 19 # CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23]
|
| D | load-store-acquire-release-v8.txt | 18 # CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 19 # CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23]
|
| D | load-store-acquire-release-v8.txt | 18 # CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/AtomicExpand/ARM/ |
| D | atomic-expansion-v8.ll | 75 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
|
| /external/llvm/test/Transforms/AtomicExpand/ARM/ |
| D | atomic-expansion-v8.ll | 75 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3284 void stlexd(Condition cond,
3289 void stlexd(Register rd, in stlexd() function
3293 stlexd(al, rd, rt, rt2, operand); in stlexd()
|
| D | disasm-aarch32.h | 1211 void stlexd(Condition cond,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3413 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
|
| D | ARMInstrInfo.td | 5013 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3431 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
|
| D | ARMInstrInfo.td | 4748 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7761 "stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005stmib\003"
8824 …{ 1326 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_Is…
8825 …{ 1326 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, …
|