/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | load-store-acquire-release-v8.s | 18 stlexh r4, r2, [r5] 22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
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D | load-store-acquire-release-v8-thumb.s | 18 stlexh r4, r2, [r5] 22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
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D | thumbv8m.s | 136 stlexh r1, r2, [r3] label
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/external/llvm/test/MC/ARM/ |
D | load-store-acquire-release-v8.s | 18 stlexh r4, r2, [r5] 22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
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D | load-store-acquire-release-v8-thumb.s | 18 stlexh r4, r2, [r5] 22 @ CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
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D | thumbv8m.s | 136 stlexh r1, r2, [r3] label
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/external/capstone/suite/MC/ARM/ |
D | load-store-acquire-release-v8-thumb.s.cs | 7 0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5]
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D | load-store-acquire-release-v8.s.cs | 7 0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5]
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/external/llvm/test/MC/Disassembler/ARM/ |
D | load-store-acquire-release-v8-thumb.txt | 17 # CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
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D | load-store-acquire-release-v8.txt | 16 # CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | load-store-acquire-release-v8-thumb.txt | 17 # CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
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D | load-store-acquire-release-v8.txt | 16 # CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | ldaex-stlex.ll | 76 ; CHECK: stlexh r0, r1, [r2]
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D | atomic-ops-v8.ll | 143 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 431 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 525 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] 622 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]] 1085 ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
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/external/llvm/test/CodeGen/ARM/ |
D | ldaex-stlex.ll | 76 ; CHECK: stlexh r0, r1, [r2]
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D | atomic-ops-v8.ll | 143 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 431 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 525 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] 622 ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]] 1084 ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3296 void stlexh(Condition cond, 3300 void stlexh(Register rd, Register rt, const MemOperand& operand) { in stlexh() function 3301 stlexh(al, rd, rt, operand); in stlexh()
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D | disasm-aarch32.h | 1217 void stlexh(Condition cond,
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D | disasm-aarch32.cc | 2995 void Disassembler::stlexh(Condition cond, in stlexh() function in vixl::aarch32::Disassembler 10099 stlexh(CurrentCond(), in DecodeT32() 58103 stlexh(condition, in DecodeA32()
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D | assembler-aarch32.cc | 11058 void Assembler::stlexh(Condition cond, in stlexh() function in vixl::aarch32::Assembler 11085 Delegate(kStlexh, &Assembler::stlexh, cond, rd, rt, operand); in stlexh()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 3386 "stlexh", "\t$Rd, $Rt, $addr", "",
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D | ARMInstrInfo.td | 5003 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 3404 "stlexh", "\t$Rd, $Rt, $addr", "",
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D | ARMInstrInfo.td | 4738 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 7761 "stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005stmib\003" 8826 …{ 1333 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_… 8827 …{ 1333 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_Is…
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