| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 9 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
31 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
46 # CHECK: %1:sreg_128 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
51 # CHECK: S_NOP 0, implicit %1.sub3
60 # CHECK: S_NOP 0, implicit undef %4.sub3
91 %1 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
96 S_NOP 0, implicit %1.sub3
105 S_NOP 0, implicit %4.sub3
130 # CHECK: S_NOP 0, implicit %3.sub3
145 # CHECK: S_NOP 0, implicit %12.sub3
[all …]
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| D | splitkit.mir | 22 S_NOP 0, implicit-def %0.sub3 : sreg_128
28 S_NOP 0, implicit %0.sub3
30 S_NOP 0, implicit %0.sub3
79 S_NOP 0, implicit-def %0.sub3 : sreg_128
102 S_NOP 0, implicit %0.sub3
104 S_NOP 0, implicit %0.sub3
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| D | rename-independent-subregs-mac-operands.mir | 80 # GCN: undef %6.sub3:vreg_128 = V_ADD_F32_e32 undef %3:vgpr_32, undef %3:vgpr_32, implicit $exec
84 # GCN: BUFFER_STORE_DWORD_OFFEN %6.sub3, %0,
122 %6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit $exec
128 …BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, implicit $exec
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| D | regcoal-subrange-join.mir | 116 %31 = V_ADD_F32_e32 %30, %1.sub3, implicit $exec
123 %56.sub3 = COPY killed %31
144 %44 = V_ADD_F32_e32 %43, %7.sub3, implicit $exec
151 %57.sub3 = COPY killed %44
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| D | subreg_interference.mir | 25 S_NOP 0, implicit-def %0.sub3
30 S_NOP 0, implicit %0.sub0, implicit %0.sub3
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| D | coalescer-subreg-join.mir | 58 %11.sub3 = COPY %1
67 %20.sub3 = COPY %2
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| D | coalescer-subranges-another-prune-error.mir | 31 %2.sub3:sreg_128 = COPY %1
176 %59.sub3:vreg_128 = COPY killed %82.sub3
246 %105:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-rel32-lo) 0, %20.sub3, implicit $exec
255 %109.sub3:sreg_256 = COPY %108
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| D | coalescer-subranges-another-copymi-not-live.mir | 48 %9.sub3:sreg_128 = COPY killed %8
59 %12.sub3:sreg_128 = COPY killed %11
123 %27.sub3:sreg_256 = COPY %26
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 42 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
62 # CHECK: S_NOP 0, implicit %1:sub3
71 # CHECK: S_NOP 0, implicit undef %4:sub3
103 %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
108 S_NOP 0, implicit %1:sub3
117 S_NOP 0, implicit %4:sub3
142 # CHECK: S_NOP 0, implicit %3:sub3
157 # CHECK: S_NOP 0, implicit %12:sub3
192 S_NOP 0, implicit %3:sub3
207 S_NOP 0, implicit %12:sub3
[all …]
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| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/analysis/ |
| D | CommonSuperclassTest.java | 208 String sub3 = "Liface/sub3;"; in testGetCommonSuperclass_interfaces() local
226 superclassTest(base1, base1, sub3); in testGetCommonSuperclass_interfaces()
233 superclassTest(object, sub3, iface1); in testGetCommonSuperclass_interfaces()
250 superclassTest(sub3, sub3, classsub3); in testGetCommonSuperclass_interfaces()
253 superclassTest(sub3, sub3, classsub4); in testGetCommonSuperclass_interfaces()
261 superclassTest(sub3, sub3, classsub1234); in testGetCommonSuperclass_interfaces()
264 superclassTest(unknown, sub3, classsub1); in testGetCommonSuperclass_interfaces()
266 superclassTest(unknown, sub3, classsub2); in testGetCommonSuperclass_interfaces()
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| /external/sfntly/cpp/src/test/ |
| D | bitmap_table_test.cc | 112 IndexSubTableFormat3Ptr sub3 = in TestReadingBitmapTable() local
114 EXPECT_FALSE(sub3 == NULL); in TestReadingBitmapTable()
116 info.Attach(sub3->GlyphInfo(2)); in TestReadingBitmapTable()
182 IndexSubTableFormat3Ptr sub3 = in TestIndexFormatConversion() local
184 EXPECT_FALSE(sub3 == NULL); in TestIndexFormatConversion()
191 original_info.Attach(sub3->GlyphInfo(i)); in TestIndexFormatConversion()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | expand-condsets-extend.ll | 53 %aSig0.3554 = phi i64 [ %aSig0.3.ph, %while.body.lr.ph ], [ %sub3.i205, %exit312 ]
79 %sub3.i205 = sub i64 %sub1.i202, %or10.i
87 …%aSig0.3.lcssa = phi i64 [ %aSig0.3.ph, %while.cond.preheader ], [ %sub3.i205, %while.end.loopexit…
99 %aSig0.5 = phi i64 [ %sub3.i151, %do.body ], [ %shr8.i155, %if.else71 ]
103 %sub3.i151 = add i64 %sub1.i148, 0
104 %cmp73 = icmp sgt i64 %sub3.i151, -1
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| D | swp-dag-phi.ll | 30 %sub3 = sub nsw i32 %sr17, %1
31 store i32 %sub3, i32* %arrayidx, align 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GVNHoist/ |
| D | hoist.ll | 30 %sub3 = fsub float %max, %a
31 %mul4 = fmul float %sub3, %div
77 %sub3 = fsub float %3, %4
78 %mul4 = fmul float %sub3, %div
130 %sub3 = fsub float %3, %4
131 %mul4 = fmul float %sub3, %div
177 %sub3 = fsub float %3, %4
178 %mul4 = fmul float %sub3, %div
295 %sub3 = fsub float %3, %4
296 %mul4 = fmul float %sub3, %div
[all …]
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| D | hoist-newgvn.ll | 35 %sub3 = fsub float %3, %4
36 %mul4 = fmul float %sub3, %div
80 %sub3 = fsub float %3, %4
81 %mul4 = fmul float %sub3, %div
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Inline/ARM/ |
| D | inline-fp.ll | 66 %sub3 = fsub float %conv2, %mul
67 %div = fdiv float %sub3, %mul
91 %sub3 = fsub double %conv2, %mul
92 %div = fdiv double %sub3, %mul
104 %sub3 = fsub float %conv2, %mul
105 %div = fdiv float %sub3, %mul
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/ |
| D | 2012-06-08-InfiniteLoop.ll | 10 %c.0 = phi i32 [ undef, %entry ], [ %sub3, %while.body ]
16 %sub3 = sub nsw i32 0, %c.0
|
| /external/llvm/test/Transforms/Reassociate/ |
| D | 2012-06-08-InfiniteLoop.ll | 10 %c.0 = phi i32 [ undef, %entry ], [ %sub3, %while.body ]
16 %sub3 = sub nsw i32 0, %c.0
|
| /external/swiftshader/third_party/LLVM/test/Transforms/TailCallElim/ |
| D | dup_tail.ll | 15 %sub3 = add nsw i32 %n, -1
16 %call4 = call i32 @fib(i32 %sub3)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/TailCallElim/ |
| D | dup_tail.ll | 18 %sub3 = add nsw i32 %n, -1
19 %call4 = call i32 @fib(i32 %sub3)
|
| D | opt-remarks-recursion.ll | 16 %sub3 = add nsw i32 %n, -1
17 %call4 = call i32 @fib(i32 %sub3), !dbg !8
|
| /external/llvm/test/Transforms/TailCallElim/ |
| D | dup_tail.ll | 18 %sub3 = add nsw i32 %n, -1
19 %call4 = call i32 @fib(i32 %sub3)
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 137 def SGPR_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
144 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
155 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
186 def TTMP_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
210 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
217 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
228 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| /external/llvm/test/Transforms/Inline/ |
| D | inline-fp.ll | 113 %sub3 = fsub float %conv2, %mul
114 %div = fdiv float %sub3, %mul
126 %sub3 = fsub float %conv2, %mul
127 %div = fdiv float %sub3, %mul
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | swp-dag-phi.ll | 30 %sub3 = sub nsw i32 %sr17, %1
31 store i32 %sub3, i32* %arrayidx, align 4
|