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Searched refs:sub4 (Results 1 – 25 of 67) sorted by relevance

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/external/smali/dexlib2/src/test/java/org/jf/dexlib2/analysis/
DCommonSuperclassTest.java209 String sub4 = "Liface/sub4;"; in testGetCommonSuperclass_interfaces() local
228 superclassTest(base1, base1, sub4); in testGetCommonSuperclass_interfaces()
252 superclassTest(sub4, sub4, classsub4); in testGetCommonSuperclass_interfaces()
262 superclassTest(sub4, sub4, classsub1234); in testGetCommonSuperclass_interfaces()
265 superclassTest(unknown, sub4, classsub1); in testGetCommonSuperclass_interfaces()
267 superclassTest(unknown, sub4, classsub2); in testGetCommonSuperclass_interfaces()
269 superclassTest(unknown, sub4, base2); in testGetCommonSuperclass_interfaces()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/StructurizeCFG/
Dpost-order-traversal-bug.ll45 %sub4 = sub nsw i32 %tmp0, %prev_start.026
65 %best_count.231 = phi i32 [ %sub4, %if.then ], [ %best_count.025, %lor.lhs.false ]
79 %sub4.6 = sub nsw i32 %tmp26, %tmp22
80 %cmp5.6 = icmp slt i32 %best_count.231, %sub4.6
97 %best_count.025.be = phi i32 [ %sub4.6, %if.then6.6 ], [ %best_count.231, %for.body.6 ]
/external/llvm/test/Transforms/StructurizeCFG/
Dpost-order-traversal-bug.ll45 %sub4 = sub nsw i32 %tmp0, %prev_start.026
65 %best_count.231 = phi i32 [ %sub4, %if.then ], [ %best_count.025, %lor.lhs.false ]
79 %sub4.6 = sub nsw i32 %tmp26, %tmp22
80 %cmp5.6 = icmp slt i32 %best_count.231, %sub4.6
97 %best_count.025.be = phi i32 [ %sub4.6, %if.then6.6 ], [ %best_count.231, %for.body.6 ]
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Daddnegneg.ll8 %sub4 = add i32 %c.neg, %b.neg ; <i32> [#uses=1]
9 %sub6 = add i32 %sub4, %d ; <i32> [#uses=1]
/external/llvm/test/Transforms/InstCombine/
Daddnegneg.ll8 %sub4 = add i32 %c.neg, %b.neg ; <i32> [#uses=1]
9 %sub6 = add i32 %sub4, %d ; <i32> [#uses=1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Daddnegneg.ll8 %sub4 = add i32 %c.neg, %b.neg ; <i32> [#uses=1]
9 %sub6 = add i32 %sub4, %d ; <i32> [#uses=1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dpacketize-return-arg.ll20 %sub4 = add i32 %0, 131
21 %and5 = and i32 %sub4, -128
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dcoalescer-subreg-join.mir59 %11.sub4 = COPY %1
68 %20.sub4 = COPY %2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dphi3.ll22 %sub4 = fsub double %sub1, undef
23 %div.i16 = fdiv double %sub4, undef
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dphi3.ll22 %sub4 = fsub double %sub1, undef
23 %div.i16 = fdiv double %sub4, undef
/external/sfntly/cpp/src/test/
Dbitmap_table_test.cc168 IndexSubTableFormat4Ptr sub4 = in TestIndexFormatConversion() local
170 EXPECT_FALSE(sub4 == NULL); in TestIndexFormatConversion()
190 info.Attach(sub4->GlyphInfo(i)); in TestIndexFormatConversion()
/external/llvm/test/Transforms/Reassociate/
Dpr12245.ll25 %sub4 = sub nsw i32 %dec3, %5
26 store i32 %sub4, i32* @d, align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
Dpr12245.ll25 %sub4 = sub nsw i32 %dec3, %5
26 store i32 %sub4, i32* @d, align 4
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2011-03-02-DAGCombiner.ll36 %sub4 = fsub x86_fp80 %conv3, %tmp1
37 %conv5 = fptoui x86_fp80 %sub4 to i32
/external/llvm/test/CodeGen/X86/
D2011-03-02-DAGCombiner.ll36 %sub4 = fsub x86_fp80 %conv3, %tmp1
37 %conv5 = fptoui x86_fp80 %sub4 to i32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2011-03-02-DAGCombiner.ll36 %sub4 = fsub x86_fp80 %conv3, %tmp1
37 %conv5 = fptoui x86_fp80 %sub4 to i32
Dfmaddsub-combine.ll204 %sub4 = fsub float %A4, %B4
224 %vecinsert5 = insertelement <8 x float> %vecinsert4, float %sub4, i32 4
289 %sub4 = fsub float %A4, %B4
333 %vecinsert5 = insertelement <16 x float> %vecinsert4, float %sub4, i32 4
375 %sub4 = fsub double %A4, %B4
392 %vecinsert5 = insertelement <8 x double> %vecinsert4, double %sub4, i32 4
473 %sub4 = fadd float %A4, %B4
493 %vecinsert5 = insertelement <8 x float> %vecinsert4, float %sub4, i32 4
558 %sub4 = fadd float %A4, %B4
602 %vecinsert5 = insertelement <16 x float> %vecinsert4, float %sub4, i32 4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dstldst.ll26 %sub4 = add nsw i32 %5, -5
33 …i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %ad…
/external/llvm/test/CodeGen/Mips/
Dstldst.ll26 %sub4 = add nsw i32 %5, -5
33 …i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %ad…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-narrow-st-merge.ll156 %sub4 = add nsw i32 %n, -2
157 %idxprom5 = sext i32 %sub4 to i64
199 %sub4 = add nsw i32 %n, -2
200 %idxprom5 = sext i32 %sub4 to i64
/external/clang/test/Sema/
Dtypecheck-binop.c17 int sub4(void *P, void *Q) { in sub4() function
/external/llvm/lib/Target/AMDGPU/
DAMDGPURegisterInfo.cpp41 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, in getSubRegFromChannel()
DSIRegisterInfo.td144 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
155 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
217 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
228 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/LoopAccessAnalysis/
Dpr31098.ll93 %sub4.i = fsub fast float %2, %5
95 store float %sub4.i, float* %imaginary_.i.i28, align 4
/external/llvm/test/CodeGen/SystemZ/
Dfp-sub-01.ll110 %sub4 = fsub float %sub3, %val4
111 %sub5 = fsub float %sub4, %val5

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