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Searched refs:subslices (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/intel/common/
Dgen_device_info.c693 #define subslices(args...) { args, } macro
705 GEN10_FEATURES(1, 1, subslices(2), 2),
711 GEN10_FEATURES(1, 1, subslices(3), 3),
717 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
723 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_program.c387 unsigned subslices = MAX2(brw->screen->subslice_total, 1); in brw_alloc_stage_scratch() local
403 subslices = 4 * brw->screen->devinfo.num_slices; in brw_alloc_stage_scratch()
433 thread_count = scratch_ids_per_subslice * subslices; in brw_alloc_stage_scratch()
DgenX_state_upload.c4235 const uint32_t subslices = MAX2(brw->screen->subslice_total, 1); local
4236 vfe.MaximumNumberofThreads = devinfo->max_cs_threads * subslices - 1;
/external/skqp/src/compute/hs/vk/intel/gen8/u64/
Dgen.bat31 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skia/src/compute/hs/vk/intel/gen8/u32/
Dgen.bat34 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skia/src/compute/hs/vk/intel/gen8/u64/
Dgen.bat31 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skqp/src/compute/hs/vk/intel/gen8/u32/
Dgen.bat34 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skqp/src/compute/hs/cl/intel/gen8/u32/
Dgen.bat17 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skia/src/compute/hs/cl/intel/gen8/u64/
Dgen.bat14 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skia/src/compute/hs/cl/intel/gen8/u32/
Dgen.bat17 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/skqp/src/compute/hs/cl/intel/gen8/u64/
Dgen.bat14 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
/external/mesa3d/src/intel/vulkan/
Danv_allocator.c1100 const unsigned subslices = MAX2(physical_device->subslice_total, 1); in anv_scratch_pool_alloc() local
1136 [MESA_SHADER_COMPUTE] = scratch_ids_per_subslice * subslices, in anv_scratch_pool_alloc()
DgenX_pipeline.c1810 const uint32_t subslices = MAX2(physical_device->subslice_total, 1); local
1822 devinfo->max_cs_threads * subslices - 1;
/external/python/cpython2/Doc/library/
Drandom.rst183 subslices).
/external/python/cpython3/Doc/library/
Drandom.rst201 subslices).