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Searched refs:sys_pll2_cfg0 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c113 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); in decode_sscg_pll()
630 pll_cfg0 = &ana_pll->sys_pll2_cfg0; in sscg_pll_init()
713 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK | in clock_init()
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dimx-regs.h222 u32 sys_pll2_cfg0; member